Lines Matching refs:reg
75 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
76 #define A7MODE(reg) GET_BITFIELD(reg, 26, 26)
143 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
146 return GET_BITFIELD(reg, table[interleave].start,
161 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
162 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
168 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
170 #define SOURCE_ID_KNL(reg) GET_BITFIELD(reg, 12, 14)
183 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
184 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
185 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
186 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
187 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
188 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
189 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
203 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
224 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
225 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
232 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
233 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
245 #define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \
246 GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19))
248 #define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \
249 GET_BITFIELD(reg, 2, 15) : GET_BITFIELD(reg, 2, 14))
257 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
258 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
259 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
260 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
272 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
273 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
320 u64 (*rir_limit)(u32 reg);
321 u64 (*sad_limit)(u32 reg);
322 u32 (*interleave_mode)(u32 reg);
323 u32 (*dram_attr)(u32 reg);
796 u32 reg;
799 pci_read_config_dword(pvt->pci_sad1, TOLM, ®);
800 return GET_TOLM(reg);
805 u32 reg;
807 pci_read_config_dword(pvt->pci_sad1, TOHM, ®);
808 return GET_TOHM(reg);
813 u32 reg;
815 pci_read_config_dword(pvt->pci_br1, TOLM, ®);
817 return GET_TOLM(reg);
822 u32 reg;
824 pci_read_config_dword(pvt->pci_br1, TOHM, ®);
826 return GET_TOHM(reg);
829 static u64 rir_limit(u32 reg)
831 return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff;
834 static u64 sad_limit(u32 reg)
836 return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff;
839 static u32 interleave_mode(u32 reg)
841 return GET_BITFIELD(reg, 1, 1);
844 static u32 dram_attr(u32 reg)
846 return GET_BITFIELD(reg, 2, 3);
849 static u64 knl_sad_limit(u32 reg)
851 return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff;
854 static u32 knl_interleave_mode(u32 reg)
856 return GET_BITFIELD(reg, 1, 2);
863 static const char *get_intlv_mode_str(u32 reg, enum type t)
866 return knl_intlv_mode[knl_interleave_mode(reg)];
868 return interleave_mode(reg) ? "[8:6]" : "[8:6]XOR[18:16]";
871 static u32 dram_attr_knl(u32 reg)
873 return GET_BITFIELD(reg, 3, 4);
879 u32 reg;
884 ®);
885 if (GET_BITFIELD(reg, 11, 11))
898 u32 reg;
906 HASWELL_DDRCRCLKCONTROLS, ®);
908 if (GET_BITFIELD(reg, 16, 16))
911 pci_read_config_dword(pvt->pci_ta, MCMTR, ®);
912 if (GET_BITFIELD(reg, 14, 14)) {
982 u32 reg;
983 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®);
984 return GET_BITFIELD(reg, 0, 2);
989 u32 reg;
991 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®);
992 return GET_BITFIELD(reg, 0, 3);
997 u32 reg;
999 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®);
1000 return GET_BITFIELD(reg, 0, 2);
1039 u32 reg;
1041 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®);
1042 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1048 u32 reg;
1050 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®);
1051 rc = GET_BITFIELD(reg, 26, 31);
1052 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®);
1053 rc = ((reg << 6) | rc) << 26;
1060 u32 reg;
1062 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, ®);
1063 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1078 static u64 haswell_rir_limit(u32 reg)
1080 return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1;
1227 static u32 knl_get_edc_route(int entry, u32 reg)
1230 return GET_BITFIELD(reg, entry*3, (entry*3)+2);
1250 static u32 knl_get_mc_route(int entry, u32 reg)
1256 mc = GET_BITFIELD(reg, entry*3, (entry*3)+2);
1257 chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1);
1266 static void knl_show_edc_route(u32 reg, char *s)
1271 s[i*2] = knl_get_edc_route(i, reg) + '0';
1282 static void knl_show_mc_route(u32 reg, char *s)
1287 s[i*2] = knl_get_mc_route(i, reg) + '0';
1298 #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29)
1301 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1304 #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29)
1307 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1310 #define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27)
1566 u32 reg;
1570 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®);
1572 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®);
1575 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg);
1577 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
1679 u32 reg;
1703 if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®)) {
1707 pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);
1708 if (GET_BITFIELD(reg, 28, 28)) {
1714 if (pci_read_config_dword(pvt->pci_ras, RASENABLES, ®)) {
1718 if (IS_MIRROR_ENABLED(reg)) {
1756 u32 reg;
1791 ®);
1792 limit = pvt->info.sad_limit(reg);
1794 if (!DRAM_RULE_ENABLE(reg))
1802 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
1804 show_dram_attr(pvt->info.dram_attr(reg)),
1807 get_intlv_mode_str(reg, pvt->info.type),
1808 reg);
1812 ®);
1813 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1815 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1832 pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], ®);
1833 limit = TAD_LIMIT(reg);
1839 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
1842 (u32)(1 << TAD_SOCK(reg)),
1843 (u32)TAD_CH(reg) + 1,
1844 (u32)TAD_TGT0(reg),
1845 (u32)TAD_TGT1(reg),
1846 (u32)TAD_TGT2(reg),
1847 (u32)TAD_TGT3(reg),
1848 reg);
1861 ®);
1862 tmp_mb = TAD_OFFSET(reg) >> 20;
1864 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1868 reg);
1881 ®);
1883 if (!IS_RIR_VALID(reg))
1886 tmp_mb = pvt->info.rir_limit(reg) >> 20;
1887 rir_way = 1 << RIR_WAY(reg);
1889 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1894 reg);
1899 ®);
1900 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6;
1903 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1907 (u32)RIR_RNK_TGT(pvt->info.type, reg),
1908 reg);
1939 u32 reg, dram_rule;
1968 ®);
1970 if (!DRAM_RULE_ENABLE(reg))
1973 limit = pvt->info.sad_limit(reg);
1986 dram_rule = reg;
1991 ®);
1994 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1996 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
2050 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2056 pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®);
2057 shiftup = GET_BITFIELD(reg, 22, 22);
2065 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2093 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®);
2094 limit = TAD_LIMIT(reg);
2108 ch_way = TAD_CH(reg) + 1;
2109 sck_way = TAD_SOCK(reg);
2125 base_ch = TAD_TGT0(reg);
2128 base_ch = TAD_TGT1(reg);
2131 base_ch = TAD_TGT2(reg);
2134 base_ch = TAD_TGT3(reg);
2198 pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], ®);
2200 if (!IS_RIR_VALID(reg))
2203 limit = pvt->info.rir_limit(reg);
2209 1 << RIR_WAY(reg));
2218 rir_way = RIR_WAY(reg);
2226 pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®);
2227 *rank = RIR_RNK_TGT(pvt->info.type, reg);
2244 u32 reg, channel = GET_BITFIELD(m->status, 0, 3);
2275 pci_read_config_dword(pci_ha, tad_dram_rule[0], ®);
2276 tad0 = m->addr <= TAD_LIMIT(reg);