Lines Matching refs:pvt
318 u64 (*get_tolm)(struct sbridge_pvt *pvt);
319 u64 (*get_tohm)(struct sbridge_pvt *pvt);
328 u8 (*get_node_id)(struct sbridge_pvt *pvt);
330 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
331 enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
794 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
799 pci_read_config_dword(pvt->pci_sad1, TOLM, ®);
803 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
807 pci_read_config_dword(pvt->pci_sad1, TOHM, ®);
811 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
815 pci_read_config_dword(pvt->pci_br1, TOLM, ®);
820 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
824 pci_read_config_dword(pvt->pci_br1, TOHM, ®);
877 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
882 if (pvt->pci_ddrio) {
883 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
896 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
902 if (!pvt->pci_ddrio)
905 pci_read_config_dword(pvt->pci_ddrio,
911 pci_read_config_dword(pvt->pci_ta, MCMTR, ®);
928 static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr)
934 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
959 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
968 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)
974 static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt)
980 static u8 get_node_id(struct sbridge_pvt *pvt)
983 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®);
987 static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
991 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®);
995 static u8 knl_get_node_id(struct sbridge_pvt *pvt)
999 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®);
1037 static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
1041 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®);
1045 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
1050 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®);
1052 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®);
1058 static u64 knl_get_tolm(struct sbridge_pvt *pvt)
1062 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, ®);
1066 static u64 knl_get_tohm(struct sbridge_pvt *pvt)
1071 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, ®_lo);
1072 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, ®_hi);
1135 * @pvt: driver private data
1146 static int knl_get_tad(const struct sbridge_pvt *pvt,
1159 pci_mc = pvt->knl.pci_mc0;
1162 pci_mc = pvt->knl.pci_mc1;
1340 static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes)
1367 pci_read_config_dword(pvt->knl.pci_cha[i],
1393 pci_read_config_dword(pvt->knl.pci_cha[i],
1416 for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) {
1420 pci_read_config_dword(pvt->pci_sad0,
1421 pvt->info.dram_rule[sad_rule], &dram_rule);
1428 sad_limit = pvt->info.sad_limit(dram_rule)+1;
1430 pci_read_config_dword(pvt->pci_sad0,
1431 pvt->info.interleave_list[sad_rule], &interleave_reg);
1437 first_pkg = sad_pkg(pvt->info.interleave_pkg,
1440 pkg = sad_pkg(pvt->info.interleave_pkg,
1484 if (knl_get_tad(pvt,
1565 struct sbridge_pvt *pvt = mci->pvt_info;
1568 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
1569 pvt->info.type == KNIGHTS_LANDING)
1570 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®);
1572 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®);
1574 if (pvt->info.type == KNIGHTS_LANDING)
1575 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg);
1577 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
1584 struct sbridge_pvt *pvt = mci->pvt_info;
1585 int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS
1592 mtype = pvt->info.get_memory_type(pvt);
1610 if (pvt->info.type == KNIGHTS_LANDING) {
1612 if (!pvt->knl.pci_channel[i])
1616 if (!pvt->pci_tad[i])
1622 if (pvt->info.type == KNIGHTS_LANDING) {
1623 pci_read_config_dword(pvt->knl.pci_channel[i],
1626 pci_read_config_dword(pvt->pci_tad[i],
1631 if (!IS_ECC_ENABLED(pvt->info.mcmtr)) {
1633 pvt->sbridge_dev->source_id,
1634 pvt->sbridge_dev->dom, i);
1637 pvt->channel[i].dimms++;
1639 ranks = numrank(pvt->info.type, mtr);
1641 if (pvt->info.type == KNIGHTS_LANDING) {
1655 pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j,
1661 dimm->dtype = pvt->info.get_width(pvt, mtr);
1666 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j);
1676 struct sbridge_pvt *pvt = mci->pvt_info;
1681 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
1683 pvt->sbridge_dev->mc,
1684 pvt->sbridge_dev->node_id,
1685 pvt->sbridge_dev->source_id);
1690 if (pvt->info.type == KNIGHTS_LANDING) {
1692 pvt->mirror_mode = NON_MIRRORING;
1693 pvt->is_cur_addr_mirrored = false;
1695 if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0)
1697 if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) {
1702 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
1703 if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®)) {
1707 pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);
1709 pvt->mirror_mode = ADDR_RANGE_MIRRORING;
1714 if (pci_read_config_dword(pvt->pci_ras, RASENABLES, ®)) {
1719 pvt->mirror_mode = FULL_MIRRORING;
1722 pvt->mirror_mode = NON_MIRRORING;
1727 if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) {
1731 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
1734 pvt->is_lockstep = true;
1738 pvt->is_lockstep = false;
1740 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
1742 pvt->is_close_pg = true;
1745 pvt->is_close_pg = false;
1754 struct sbridge_pvt *pvt = mci->pvt_info;
1766 pvt->tolm = pvt->info.get_tolm(pvt);
1767 tmp_mb = (1 + pvt->tolm) >> 20;
1771 gb, (mb*1000)/1024, (u64)pvt->tolm);
1774 pvt->tohm = pvt->info.get_tohm(pvt);
1775 tmp_mb = (1 + pvt->tohm) >> 20;
1779 gb, (mb*1000)/1024, (u64)pvt->tohm);
1788 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1790 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1792 limit = pvt->info.sad_limit(reg);
1804 show_dram_attr(pvt->info.dram_attr(reg)),
1807 get_intlv_mode_str(reg, pvt->info.type),
1811 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1813 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1815 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1824 if (pvt->info.type == KNIGHTS_LANDING)
1832 pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], ®);
1856 if (!pvt->channel[i].dimms)
1859 pci_read_config_dword(pvt->pci_tad[i],
1876 if (!pvt->channel[i].dimms)
1879 pci_read_config_dword(pvt->pci_tad[i],
1886 tmp_mb = pvt->info.rir_limit(reg) >> 20;
1897 pci_read_config_dword(pvt->pci_tad[i],
1900 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6;
1907 (u32)RIR_RNK_TGT(pvt->info.type, reg),
1933 struct sbridge_pvt *pvt = mci->pvt_info;
1954 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
1958 if (addr >= (u64)pvt->tohm) {
1966 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1967 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1973 limit = pvt->info.sad_limit(reg);
1982 if (n_sads == pvt->info.max_sad) {
1987 *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule));
1988 interleave_mode = pvt->info.interleave_mode(dram_rule);
1990 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1993 if (pvt->info.type == SANDY_BRIDGE) {
1994 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1996 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
2004 pvt->sbridge_dev->mc,
2033 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
2050 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2056 pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®);
2065 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2085 pvt = mci->pvt_info;
2091 pci_ha = pvt->pci_ha;
2115 if (pvt->is_chan_hash)
2142 pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset);
2144 if (pvt->mirror_mode == FULL_MIRRORING ||
2145 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && n_tads == 0)) {
2157 pvt->is_cur_addr_mirrored = true;
2160 pvt->is_cur_addr_mirrored = false;
2163 if (pvt->is_lockstep)
2198 pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], ®);
2203 limit = pvt->info.rir_limit(reg);
2220 if (pvt->is_close_pg)
2226 pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®);
2227 *rank = RIR_RNK_TGT(pvt->info.type, reg);
2246 struct sbridge_pvt *pvt;
2255 pvt = mci->pvt_info;
2256 if (!pvt->info.get_ha) {
2260 *ha = pvt->info.get_ha(m->bank);
2273 pvt = new_mci->pvt_info;
2274 pci_ha = pvt->pci_ha;
2279 if (pvt->mirror_mode == FULL_MIRRORING ||
2280 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && tad0)) {
2282 pvt->is_cur_addr_mirrored = true;
2284 pvt->is_cur_addr_mirrored = false;
2287 if (pvt->is_lockstep)
2489 struct sbridge_pvt *pvt = mci->pvt_info;
2501 pvt->pci_sad0 = pdev;
2504 pvt->pci_sad1 = pdev;
2507 pvt->pci_br0 = pdev;
2510 pvt->pci_ha = pdev;
2513 pvt->pci_ta = pdev;
2516 pvt->pci_ras = pdev;
2524 pvt->pci_tad[id] = pdev;
2529 pvt->pci_ddrio = pdev;
2542 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha ||
2543 !pvt->pci_ras || !pvt->pci_ta)
2563 struct sbridge_pvt *pvt = mci->pvt_info;
2576 pvt->pci_ha = pdev;
2580 pvt->pci_ta = pdev;
2584 pvt->pci_ras = pdev;
2596 pvt->pci_tad[id] = pdev;
2601 pvt->pci_ddrio = pdev;
2604 pvt->pci_ddrio = pdev;
2607 pvt->pci_sad0 = pdev;
2610 pvt->pci_br0 = pdev;
2613 pvt->pci_br1 = pdev;
2626 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 ||
2627 !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta)
2649 struct sbridge_pvt *pvt = mci->pvt_info;
2655 if (pvt->info.pci_vtd == NULL)
2657 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2668 pvt->pci_sad0 = pdev;
2671 pvt->pci_sad1 = pdev;
2675 pvt->pci_ha = pdev;
2679 pvt->pci_ta = pdev;
2683 pvt->pci_ras = pdev;
2695 pvt->pci_tad[id] = pdev;
2703 if (!pvt->pci_ddrio)
2704 pvt->pci_ddrio = pdev;
2717 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||
2718 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
2734 struct sbridge_pvt *pvt = mci->pvt_info;
2740 if (pvt->info.pci_vtd == NULL)
2742 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2753 pvt->pci_sad0 = pdev;
2756 pvt->pci_sad1 = pdev;
2760 pvt->pci_ha = pdev;
2764 pvt->pci_ta = pdev;
2768 pvt->pci_ras = pdev;
2780 pvt->pci_tad[id] = pdev;
2785 pvt->pci_ddrio = pdev;
2798 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||
2799 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
2815 struct sbridge_pvt *pvt = mci->pvt_info;
2834 pvt->knl.pci_mc0 = pdev;
2836 pvt->knl.pci_mc1 = pdev;
2846 pvt->pci_sad0 = pdev;
2850 pvt->pci_sad1 = pdev;
2866 WARN_ON(pvt->knl.pci_cha[devidx] != NULL);
2868 pvt->knl.pci_cha[devidx] = pdev;
2891 WARN_ON(pvt->knl.pci_channel[devidx] != NULL);
2892 pvt->knl.pci_channel[devidx] = pdev;
2896 pvt->knl.pci_mc_info = pdev;
2900 pvt->pci_ta = pdev;
2910 if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 ||
2911 !pvt->pci_sad0 || !pvt->pci_sad1 ||
2912 !pvt->pci_ta) {
2917 if (!pvt->knl.pci_channel[i]) {
2924 if (!pvt->knl.pci_cha[i]) {
2951 struct sbridge_pvt *pvt = mci->pvt_info;
2974 if (pvt->info.type != SANDY_BRIDGE)
3022 if (pvt->info.type == KNIGHTS_LANDING) {
3071 pvt = mci->pvt_info;
3090 if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg)
3223 struct sbridge_pvt *pvt;
3236 sizeof(*pvt));
3244 pvt = mci->pvt_info;
3245 memset(pvt, 0, sizeof(*pvt));
3248 pvt->sbridge_dev = sbridge_dev;
3259 pvt->info.type = type;
3262 pvt->info.rankcfgr = IB_RANK_CFG_A;
3263 pvt->info.get_tolm = ibridge_get_tolm;
3264 pvt->info.get_tohm = ibridge_get_tohm;
3265 pvt->info.dram_rule = ibridge_dram_rule;
3266 pvt->info.get_memory_type = get_memory_type;
3267 pvt->info.get_node_id = get_node_id;
3268 pvt->info.get_ha = ibridge_get_ha;
3269 pvt->info.rir_limit = rir_limit;
3270 pvt->info.sad_limit = sad_limit;
3271 pvt->info.interleave_mode = interleave_mode;
3272 pvt->info.dram_attr = dram_attr;
3273 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3274 pvt->info.interleave_list = ibridge_interleave_list;
3275 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3276 pvt->info.get_width = ibridge_get_width;
3284 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3287 pvt->info.rankcfgr = SB_RANK_CFG_A;
3288 pvt->info.get_tolm = sbridge_get_tolm;
3289 pvt->info.get_tohm = sbridge_get_tohm;
3290 pvt->info.dram_rule = sbridge_dram_rule;
3291 pvt->info.get_memory_type = get_memory_type;
3292 pvt->info.get_node_id = get_node_id;
3293 pvt->info.get_ha = sbridge_get_ha;
3294 pvt->info.rir_limit = rir_limit;
3295 pvt->info.sad_limit = sad_limit;
3296 pvt->info.interleave_mode = interleave_mode;
3297 pvt->info.dram_attr = dram_attr;
3298 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
3299 pvt->info.interleave_list = sbridge_interleave_list;
3300 pvt->info.interleave_pkg = sbridge_interleave_pkg;
3301 pvt->info.get_width = sbridge_get_width;
3309 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3313 pvt->info.get_tolm = haswell_get_tolm;
3314 pvt->info.get_tohm = haswell_get_tohm;
3315 pvt->info.dram_rule = ibridge_dram_rule;
3316 pvt->info.get_memory_type = haswell_get_memory_type;
3317 pvt->info.get_node_id = haswell_get_node_id;
3318 pvt->info.get_ha = ibridge_get_ha;
3319 pvt->info.rir_limit = haswell_rir_limit;
3320 pvt->info.sad_limit = sad_limit;
3321 pvt->info.interleave_mode = interleave_mode;
3322 pvt->info.dram_attr = dram_attr;
3323 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3324 pvt->info.interleave_list = ibridge_interleave_list;
3325 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3326 pvt->info.get_width = ibridge_get_width;
3334 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3338 pvt->info.get_tolm = haswell_get_tolm;
3339 pvt->info.get_tohm = haswell_get_tohm;
3340 pvt->info.dram_rule = ibridge_dram_rule;
3341 pvt->info.get_memory_type = haswell_get_memory_type;
3342 pvt->info.get_node_id = haswell_get_node_id;
3343 pvt->info.get_ha = ibridge_get_ha;
3344 pvt->info.rir_limit = haswell_rir_limit;
3345 pvt->info.sad_limit = sad_limit;
3346 pvt->info.interleave_mode = interleave_mode;
3347 pvt->info.dram_attr = dram_attr;
3348 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3349 pvt->info.interleave_list = ibridge_interleave_list;
3350 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3351 pvt->info.get_width = broadwell_get_width;
3359 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3362 /* pvt->info.rankcfgr == ??? */
3363 pvt->info.get_tolm = knl_get_tolm;
3364 pvt->info.get_tohm = knl_get_tohm;
3365 pvt->info.dram_rule = knl_dram_rule;
3366 pvt->info.get_memory_type = knl_get_memory_type;
3367 pvt->info.get_node_id = knl_get_node_id;
3368 pvt->info.get_ha = knl_get_ha;
3369 pvt->info.rir_limit = NULL;
3370 pvt->info.sad_limit = knl_sad_limit;
3371 pvt->info.interleave_mode = knl_interleave_mode;
3372 pvt->info.dram_attr = dram_attr_knl;
3373 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule);
3374 pvt->info.interleave_list = knl_interleave_list;
3375 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3376 pvt->info.get_width = knl_get_width;
3383 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);