Lines Matching defs:interleave
144 int interleave)
146 return GET_BITFIELD(reg, table[interleave].start,
147 table[interleave].end);
1140 * @ways: output number of interleave ways
1214 * (This is the per-tile mapping of logical interleave targets to
1235 * (This is the per-tile mapping of logical interleave targets to
1316 * have to figure this out from the SAD rules, interleave lists, route tables,
1448 edac_dbg(0, "Unexpected interleave target %d\n",
1459 edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n",
1524 /* Figure out which channels participate in interleave. */
1783 * TAD registers contain the interleave wayness. However, it
1819 edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
1839 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
2000 edac_dbg(0, "SAD interleave #%d: %d\n",
2027 sprintf(msg, "Can't discover socket interleave");
2031 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
2044 /* interleave mode will XOR {8,7,6} with {18,17,16} */
2060 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
2063 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
2068 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
2168 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
2229 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",