Lines Matching defs:info
387 struct sbridge_info info;
883 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
1041 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®);
1050 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®);
1052 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®);
1416 for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) {
1421 pvt->info.dram_rule[sad_rule], &dram_rule);
1428 sad_limit = pvt->info.sad_limit(dram_rule)+1;
1431 pvt->info.interleave_list[sad_rule], &interleave_reg);
1437 first_pkg = sad_pkg(pvt->info.interleave_pkg,
1440 pkg = sad_pkg(pvt->info.interleave_pkg,
1568 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
1569 pvt->info.type == KNIGHTS_LANDING)
1574 if (pvt->info.type == KNIGHTS_LANDING)
1585 int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS
1592 mtype = pvt->info.get_memory_type(pvt);
1610 if (pvt->info.type == KNIGHTS_LANDING) {
1622 if (pvt->info.type == KNIGHTS_LANDING) {
1631 if (!IS_ECC_ENABLED(pvt->info.mcmtr)) {
1639 ranks = numrank(pvt->info.type, mtr);
1641 if (pvt->info.type == KNIGHTS_LANDING) {
1661 dimm->dtype = pvt->info.get_width(pvt, mtr);
1681 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
1690 if (pvt->info.type == KNIGHTS_LANDING) {
1697 if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) {
1702 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
1727 if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) {
1731 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
1740 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
1766 pvt->tolm = pvt->info.get_tolm(pvt);
1774 pvt->tohm = pvt->info.get_tohm(pvt);
1788 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1790 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1792 limit = pvt->info.sad_limit(reg);
1804 show_dram_attr(pvt->info.dram_attr(reg)),
1807 get_intlv_mode_str(reg, pvt->info.type),
1811 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1813 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1815 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1824 if (pvt->info.type == KNIGHTS_LANDING)
1886 tmp_mb = pvt->info.rir_limit(reg) >> 20;
1900 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6;
1907 (u32)RIR_RNK_TGT(pvt->info.type, reg),
1966 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1967 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1973 limit = pvt->info.sad_limit(reg);
1982 if (n_sads == pvt->info.max_sad) {
1987 *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule));
1988 interleave_mode = pvt->info.interleave_mode(dram_rule);
1990 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1993 if (pvt->info.type == SANDY_BRIDGE) {
1994 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1996 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
2033 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
2050 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2065 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2203 limit = pvt->info.rir_limit(reg);
2227 *rank = RIR_RNK_TGT(pvt->info.type, reg);
2256 if (!pvt->info.get_ha) {
2260 *ha = pvt->info.get_ha(m->bank);
2655 if (pvt->info.pci_vtd == NULL)
2657 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2718 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
2740 if (pvt->info.pci_vtd == NULL)
2742 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2799 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
2974 if (pvt->info.type != SANDY_BRIDGE)
3022 if (pvt->info.type == KNIGHTS_LANDING) {
3259 pvt->info.type = type;
3262 pvt->info.rankcfgr = IB_RANK_CFG_A;
3263 pvt->info.get_tolm = ibridge_get_tolm;
3264 pvt->info.get_tohm = ibridge_get_tohm;
3265 pvt->info.dram_rule = ibridge_dram_rule;
3266 pvt->info.get_memory_type = get_memory_type;
3267 pvt->info.get_node_id = get_node_id;
3268 pvt->info.get_ha = ibridge_get_ha;
3269 pvt->info.rir_limit = rir_limit;
3270 pvt->info.sad_limit = sad_limit;
3271 pvt->info.interleave_mode = interleave_mode;
3272 pvt->info.dram_attr = dram_attr;
3273 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3274 pvt->info.interleave_list = ibridge_interleave_list;
3275 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3276 pvt->info.get_width = ibridge_get_width;
3287 pvt->info.rankcfgr = SB_RANK_CFG_A;
3288 pvt->info.get_tolm = sbridge_get_tolm;
3289 pvt->info.get_tohm = sbridge_get_tohm;
3290 pvt->info.dram_rule = sbridge_dram_rule;
3291 pvt->info.get_memory_type = get_memory_type;
3292 pvt->info.get_node_id = get_node_id;
3293 pvt->info.get_ha = sbridge_get_ha;
3294 pvt->info.rir_limit = rir_limit;
3295 pvt->info.sad_limit = sad_limit;
3296 pvt->info.interleave_mode = interleave_mode;
3297 pvt->info.dram_attr = dram_attr;
3298 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
3299 pvt->info.interleave_list = sbridge_interleave_list;
3300 pvt->info.interleave_pkg = sbridge_interleave_pkg;
3301 pvt->info.get_width = sbridge_get_width;
3313 pvt->info.get_tolm = haswell_get_tolm;
3314 pvt->info.get_tohm = haswell_get_tohm;
3315 pvt->info.dram_rule = ibridge_dram_rule;
3316 pvt->info.get_memory_type = haswell_get_memory_type;
3317 pvt->info.get_node_id = haswell_get_node_id;
3318 pvt->info.get_ha = ibridge_get_ha;
3319 pvt->info.rir_limit = haswell_rir_limit;
3320 pvt->info.sad_limit = sad_limit;
3321 pvt->info.interleave_mode = interleave_mode;
3322 pvt->info.dram_attr = dram_attr;
3323 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3324 pvt->info.interleave_list = ibridge_interleave_list;
3325 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3326 pvt->info.get_width = ibridge_get_width;
3338 pvt->info.get_tolm = haswell_get_tolm;
3339 pvt->info.get_tohm = haswell_get_tohm;
3340 pvt->info.dram_rule = ibridge_dram_rule;
3341 pvt->info.get_memory_type = haswell_get_memory_type;
3342 pvt->info.get_node_id = haswell_get_node_id;
3343 pvt->info.get_ha = ibridge_get_ha;
3344 pvt->info.rir_limit = haswell_rir_limit;
3345 pvt->info.sad_limit = sad_limit;
3346 pvt->info.interleave_mode = interleave_mode;
3347 pvt->info.dram_attr = dram_attr;
3348 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3349 pvt->info.interleave_list = ibridge_interleave_list;
3350 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3351 pvt->info.get_width = broadwell_get_width;
3362 /* pvt->info.rankcfgr == ??? */
3363 pvt->info.get_tolm = knl_get_tolm;
3364 pvt->info.get_tohm = knl_get_tohm;
3365 pvt->info.dram_rule = knl_dram_rule;
3366 pvt->info.get_memory_type = knl_get_memory_type;
3367 pvt->info.get_node_id = knl_get_node_id;
3368 pvt->info.get_ha = knl_get_ha;
3369 pvt->info.rir_limit = NULL;
3370 pvt->info.sad_limit = knl_sad_limit;
3371 pvt->info.interleave_mode = knl_interleave_mode;
3372 pvt->info.dram_attr = dram_attr_knl;
3373 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule);
3374 pvt->info.interleave_list = knl_interleave_list;
3375 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3376 pvt->info.get_width = knl_get_width;