Lines Matching defs:channel
287 #define MAX_DIMMS 3 /* Max DIMMS per channel */
388 struct sbridge_channel channel[NUM_CHANNELS];
508 * - 3 DDR3 channels, 2 DPC per channel
511 * - 4 DDR4 channels, 3 DPC per channel
514 * - 4 DDR4 channels, 3 DPC per channel
517 * - each IMC interfaces with a SMI 2 channel
518 * - each SMI channel interfaces with a scalable memory buffer
585 /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */
625 * - 2 DDR3 channels, 2 DPC per channel
628 * - 4 DDR4 channels, 3 DPC per channel
631 * - 4 DDR4 channels, 3 DPC per channel
634 * - each IMC interfaces with a SMI 2 channel
635 * - each SMI channel interfaces with a scalable memory buffer
1016 * home agent bank (7, 8), or one of the per-channel memory
1204 /* Determine which memory controller is responsible for a given channel. */
1205 static int knl_channel_mc(int channel)
1207 WARN_ON(channel < 0 || channel >= 6);
1209 return channel < 3 ? 1 : 0;
1238 * entry 0: mc 0:2 channel 18:19
1239 * 1: mc 3:5 channel 20:21
1240 * 2: mc 6:8 channel 22:23
1241 * 3: mc 9:11 channel 24:25
1242 * 4: mc 12:14 channel 26:27
1243 * 5: mc 15:17 channel 28:29
1323 * interleaved, we know the individual contribution of each channel to
1326 * Finally, we have to check whether each channel participates in each SAD
1329 * Fortunately, KNL only supports one DIMM per channel, so once we know how
1330 * much memory the channel uses, we know the DIMM is at least that large.
1358 int channel;
1435 * We stop when we see the first channel again.
1525 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++)
1526 participants[channel] = 0;
1528 /* For each channel, does at least one CHA have
1529 * this channel mapped to the given target?
1531 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1538 mc_route_reg[cha]) == channel
1539 && !participants[channel]) {
1540 participants[channel] = 1;
1547 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1548 mc = knl_channel_mc(channel);
1549 if (participants[channel]) {
1550 edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n",
1551 channel,
1554 mc_sizes[channel] +=
1637 pvt->channel[i].dimms++;
1654 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
1853 * Step 4) Get TAD offsets, per each channel
1856 if (!pvt->channel[i].dimms)
1873 * Step 6) Get RIR Wayness/Limit, per each channel
1876 if (!pvt->channel[i].dimms)
2088 * Step 2) Get memory channel
2096 sprintf(msg, "Can't discover the memory channel");
2104 sprintf(msg, "Can't discover the memory channel");
2168 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
2179 /* Calculate channel address */
2229 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
2244 u32 reg, channel = GET_BITFIELD(m->status, 0, 3);
2250 if (channel >= NUM_CHANNELS) {
2251 sprintf(msg, "Invalid channel 0x%x", channel);
2278 *channel_mask = 1 << channel;
2281 *channel_mask |= 1 << ((channel + 2) % 4);
2288 *channel_mask |= 1 << ((channel + 1) % 4);
2482 * channel like this
2918 sbridge_printk(KERN_ERR, "Missing channel %d\n", i);
2961 u32 channel = GET_BITFIELD(m->status, 0, 3);
2998 * cccc = channel
3023 if (channel == 14) {
3034 * Reported channel is in range 0-2, so we can't map it
3039 channel = knl_channel_remap(m->bank == 16, channel);
3040 channel_mask = 1 << channel;
3043 "%s%s err_code:%04x:%04x channel:%d (DIMM_%c)",
3047 mscod, errcode, channel, A + channel);
3050 channel, 0, -1,
3087 * EDAC core should be handling the channel mask, in order to point
3091 channel = first_channel;
3105 /* FIXME: need support for channel mask */
3107 if (channel == CHANNEL_UNSPECIFIED)
3108 channel = -1;
3113 channel, dimm, -1,