Lines Matching refs:mtr
105 u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */
172 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8))
173 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7))
174 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4)
175 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4)
176 #define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0)
177 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
179 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
180 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
181 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
590 int mtr, ans, addrBits, channel;
594 mtr = pvt->mtr[slot][branch];
595 ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0;
597 edac_dbg(2, "\tMTR%d CH%d: DIMMs are %sPresent (mtr)\n",
608 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
610 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
612 addrBits += MTR_DIMM_RANKS(mtr);
620 edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
623 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
625 edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
627 MTR_DIMM_RANKS(mtr) ? "double" : "single");
629 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" :
630 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" :
631 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" :
634 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" :
635 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" :
636 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" :
657 if (MTR_DRAM_WIDTH(mtr) == 8)
664 if (MTR_DRAM_WIDTH(mtr) == 8) {
673 return mtr;
750 int mtr;
793 &pvt->mtr[slot][branch]);
801 mtr = decode_mtr(pvt, slot, ch, branch,
805 if (!MTR_DIMMS_PRESENT(mtr))