Lines Matching refs:pvt
438 struct i5400_pvt *pvt;
441 pvt = mci->pvt_info;
444 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
457 pci_read_config_dword(pvt->branchmap_werrors,
459 pci_read_config_word(pvt->branchmap_werrors,
461 pci_read_config_dword(pvt->branchmap_werrors,
465 pci_write_config_dword(pvt->branchmap_werrors,
475 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
483 pci_read_config_dword(pvt->branchmap_werrors,
485 pci_read_config_word(pvt->branchmap_werrors,
487 pci_read_config_dword(pvt->branchmap_werrors,
489 pci_read_config_dword(pvt->branchmap_werrors,
493 pci_write_config_dword(pvt->branchmap_werrors,
700 struct i5400_pvt *pvt;
702 pvt = mci->pvt_info;
705 pci_dev_put(pvt->branch_1);
706 pci_dev_put(pvt->branch_0);
707 pci_dev_put(pvt->fsb_error_regs);
708 pci_dev_put(pvt->branchmap_werrors);
719 struct i5400_pvt *pvt;
722 pvt = mci->pvt_info;
723 pvt->branchmap_werrors = NULL;
724 pvt->fsb_error_regs = NULL;
725 pvt->branch_0 = NULL;
726 pvt->branch_1 = NULL;
749 pvt->branchmap_werrors = pdev;
765 pci_dev_put(pvt->branchmap_werrors);
773 pvt->fsb_error_regs = pdev;
776 pci_name(pvt->system_address),
777 pvt->system_address->vendor, pvt->system_address->device);
779 pci_name(pvt->branchmap_werrors),
780 pvt->branchmap_werrors->vendor,
781 pvt->branchmap_werrors->device);
783 pci_name(pvt->fsb_error_regs),
784 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
786 pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL,
788 if (!pvt->branch_0) {
794 pci_dev_put(pvt->fsb_error_regs);
795 pci_dev_put(pvt->branchmap_werrors);
802 if (pvt->maxch < CHANNELS_PER_BRANCH)
805 pvt->branch_1 = pci_get_device(PCI_VENDOR_ID_INTEL,
807 if (!pvt->branch_1) {
815 pci_dev_put(pvt->branch_0);
816 pci_dev_put(pvt->fsb_error_regs);
817 pci_dev_put(pvt->branchmap_werrors);
837 static int determine_amb_present_reg(struct i5400_pvt *pvt, int channel)
843 amb_present = pvt->b0_ambpresent1;
845 amb_present = pvt->b0_ambpresent0;
848 amb_present = pvt->b1_ambpresent1;
850 amb_present = pvt->b1_ambpresent0;
857 * determine_mtr(pvt, dimm, channel)
861 static int determine_mtr(struct i5400_pvt *pvt, int dimm, int channel)
878 mtr = pvt->b0_mtr[n];
880 mtr = pvt->b1_mtr[n];
918 static void handle_channel(struct i5400_pvt *pvt, int dimm, int channel,
925 mtr = determine_mtr(pvt, dimm, channel);
927 amb_present_reg = determine_amb_present_reg(pvt, channel);
956 static void calculate_dimm_size(struct i5400_pvt *pvt)
978 max_dimms = pvt->maxdimmperch;
996 for (channel = 0; channel < pvt->maxch; channel++) {
997 dinfo = &pvt->dimm_info[dimm][channel];
998 handle_channel(pvt, dimm, channel, dinfo);
1021 for (channel = 0; channel < pvt->maxch; channel++) {
1053 struct i5400_pvt *pvt;
1059 pvt = mci->pvt_info;
1061 pci_read_config_dword(pvt->system_address, AMBASE,
1062 &pvt->u.ambase_bottom);
1063 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
1064 &pvt->u.ambase_top);
1067 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1070 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1071 pvt->tolm >>= 12;
1073 pvt->tolm, pvt->tolm);
1075 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
1077 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
1079 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1080 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
1083 limit = (pvt->mir0 >> 4) & 0x0fff;
1084 way0 = pvt->mir0 & 0x1;
1085 way1 = pvt->mir0 & 0x2;
1088 limit = (pvt->mir1 >> 4) & 0xfff;
1089 way0 = pvt->mir1 & 0x1;
1090 way1 = pvt->mir1 & 0x2;
1099 pci_read_config_word(pvt->branch_0, where,
1100 &pvt->b0_mtr[slot_row]);
1103 slot_row, where, pvt->b0_mtr[slot_row]);
1105 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1106 pvt->b1_mtr[slot_row] = 0;
1111 pci_read_config_word(pvt->branch_1, where,
1112 &pvt->b1_mtr[slot_row]);
1114 slot_row, where, pvt->b1_mtr[slot_row]);
1121 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1123 pci_read_config_word(pvt->branch_0, AMBPRESENT_0,
1124 &pvt->b0_ambpresent0);
1125 edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1126 pci_read_config_word(pvt->branch_0, AMBPRESENT_1,
1127 &pvt->b0_ambpresent1);
1128 edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1131 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1132 pvt->b1_ambpresent0 = 0;
1133 pvt->b1_ambpresent1 = 0;
1138 decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1140 pci_read_config_word(pvt->branch_1, AMBPRESENT_0,
1141 &pvt->b1_ambpresent0);
1143 pvt->b1_ambpresent0);
1144 pci_read_config_word(pvt->branch_1, AMBPRESENT_1,
1145 &pvt->b1_ambpresent1);
1147 pvt->b1_ambpresent1);
1152 calculate_dimm_size(pvt);
1166 struct i5400_pvt *pvt;
1173 pvt = mci->pvt_info;
1178 * FIXME: remove pvt->dimm_info[slot][channel] and use the 3
1184 mtr = determine_mtr(pvt, slot, channel);
1192 size_mb = pvt->dimm_info[slot][channel].megabytes;
1229 struct i5400_pvt *pvt;
1232 pvt = mci->pvt_info;
1235 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1241 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1255 struct i5400_pvt *pvt;
1283 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
1291 pvt = mci->pvt_info;
1292 pvt->system_address = pdev; /* Record this device in our private */
1293 pvt->maxch = MAX_CHANNELS;
1294 pvt->maxdimmperch = DIMMS_PER_CHANNEL;