Lines Matching refs:mtr
279 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (0x1 << 8))
280 #define MTR_DRAM_WIDTH(mtr) ((((mtr) >> 6) & 0x1) ? 8 : 4)
281 #define MTR_DRAM_BANKS(mtr) ((((mtr) >> 5) & 0x1) ? 8 : 4)
282 #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
283 #define MTR_DIMM_RANK(mtr) (((mtr) >> 4) & 0x1)
284 #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)
285 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
286 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
287 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
288 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
953 int mtr;
956 mtr = pvt->b0_mtr[slot];
958 mtr = pvt->b1_mtr[slot];
960 return mtr;
965 static void decode_mtr(int slot_row, u16 mtr)
969 ans = MTR_DIMMS_PRESENT(mtr);
972 slot_row, mtr, ans ? "" : "NOT ");
976 edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
977 edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
979 MTR_DIMM_RANK(mtr) ? "double" : "single");
981 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" :
982 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" :
983 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" :
986 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" :
987 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" :
988 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" :
995 int mtr;
999 mtr = determine_mtr(pvt, slot, channel);
1000 if (MTR_DIMMS_PRESENT(mtr)) {
1005 dinfo->dual_rank = MTR_DIMM_RANK(mtr);
1009 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
1011 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
1013 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
1253 int mtr;
1273 mtr = determine_mtr(pvt, slot, channel);
1275 if (!MTR_DIMMS_PRESENT(mtr))
1288 if (MTR_DRAM_WIDTH(mtr) == 8)