Lines Matching refs:edac_dbg
487 edac_dbg(0, "\t\tCSROW= %d Channel= %d (DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
566 edac_dbg(0, "\tUncorrected bits= 0x%x\n", ue_errors);
582 edac_dbg(0, "\t\tCSROW= %d Channels= %d,%d (Branch= %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
636 edac_dbg(0, "\tCorrected bits= 0x%x\n", ce_errors);
654 edac_dbg(0, "\t\tCSROW= %d Channel= %d (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
768 edac_dbg(4, "MC%d\n", mci->mc_idx);
839 edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x\n",
842 edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
846 edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x\n",
971 edac_dbg(2, "\tMTR%d=0x%x: DIMMs are %sPresent\n",
976 edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
977 edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
978 edac_dbg(2, "\t\tNUMRANK: %s\n",
980 edac_dbg(2, "\t\tNUMROW: %s\n",
985 edac_dbg(2, "\t\tNUMCOL: %s\n",
1064 edac_dbg(2, "%s\n", mem_buffer);
1085 edac_dbg(2, "%s\n", mem_buffer);
1095 edac_dbg(2, "%s\n", mem_buffer);
1108 edac_dbg(2, "%s\n", mem_buffer);
1121 edac_dbg(2, "%s\n", mem_buffer);
1146 edac_dbg(2, "AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n",
1152 edac_dbg(2, "TOLM (number of 256M regions) =%u (0x%x)\n",
1156 edac_dbg(2, "Actual TOLM byte addr=%u (0x%x)\n",
1167 edac_dbg(2, "MIR0: limit= 0x%x WAY1= %u WAY0= %x\n",
1172 edac_dbg(2, "MIR1: limit= 0x%x WAY1= %u WAY0= %x\n",
1177 edac_dbg(2, "MIR2: limit= 0x%x WAY1= %u WAY0= %x\n",
1187 edac_dbg(2, "MTR%d where=0x%x B0 value=0x%x\n",
1193 edac_dbg(2, "MTR%d where=0x%x B1 value=0x%x\n",
1201 edac_dbg(2, "Memory Technology Registers:\n");
1202 edac_dbg(2, " Branch 0:\n");
1208 edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1211 edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1219 edac_dbg(2, " Branch 1:\n");
1225 edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x:\n",
1229 edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x:\n",
1362 edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n",
1386 edac_dbg(0, "MC: Number of Branches=2 Channels= %d DIMMS= %d\n",
1404 edac_dbg(0, "MC: mci = %p\n", mci);
1435 edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5000_init_csrows() returned nonzero value\n");
1438 edac_dbg(1, "MC: Enable error reporting now\n");
1444 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
1487 edac_dbg(0, "MC:\n");
1506 edac_dbg(0, "\n");
1552 edac_dbg(2, "MC:\n");
1568 edac_dbg(2, "MC:\n");