Lines Matching refs:pvt
147 #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
148 #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
149 #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
152 #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
153 #define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
154 #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
157 #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
178 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
179 #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
201 #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
202 #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
204 #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
206 #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
207 #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
233 #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
234 #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
419 static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
421 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
426 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
429 static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
431 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
436 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
444 static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
446 if (pvt->fam == 0x15 && pvt->model >= 0x30)
447 return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
448 ((pvt->dct_sel_lo >> 6) & 0x3);
450 return ((pvt)->dct_sel_lo >> 6) & 0x3;
478 int (*early_channel_count) (struct amd64_pvt *pvt);
481 int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct,
521 static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
523 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
525 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
528 return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
531 static inline u8 dhar_valid(struct amd64_pvt *pvt)
533 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
535 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
538 return (pvt)->dhar & BIT(0);
541 static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
543 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
545 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
548 return (pvt)->dct_sel_lo & 0xFFFFF800;