Lines Matching refs:umc
217 if (pvt->umc) {
259 if (pvt->umc) {
723 if (pvt->umc) {
727 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT))
733 if (pvt->umc[i].umc_cfg & BIT(12))
849 struct amd64_umc *umc;
854 umc = &pvt->umc[i];
856 edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);
857 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);
858 edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);
859 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);
866 edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);
869 i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no",
870 (umc->umc_cap_hi & BIT(31)) ? "yes" : "no");
872 i, (umc->umc_cfg & BIT(12)) ? "yes" : "no");
874 i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no");
876 i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no");
928 if (pvt->umc)
950 int umc;
952 for_each_umc(umc) {
953 pvt->csels[umc].b_cnt = 4;
954 pvt->csels[umc].m_cnt = 2;
971 int cs, umc;
973 for_each_umc(umc) {
974 umc_base_reg = get_umc_base(umc) + UMCCH_BASE_ADDR;
975 umc_base_reg_sec = get_umc_base(umc) + UMCCH_BASE_ADDR_SEC;
977 for_each_chip_select(cs, umc, pvt) {
978 base = &pvt->csels[umc].csbases[cs];
979 base_sec = &pvt->csels[umc].csbases_sec[cs];
986 umc, cs, *base, base_reg);
990 umc, cs, *base_sec, base_reg_sec);
993 umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK;
994 umc_mask_reg_sec = get_umc_base(umc) + UMCCH_ADDR_MASK_SEC;
996 for_each_chip_select_mask(cs, umc, pvt) {
997 mask = &pvt->csels[umc].csmasks[cs];
998 mask_sec = &pvt->csels[umc].csmasks_sec[cs];
1005 umc, cs, *mask, mask_reg);
1009 umc, cs, *mask_sec, mask_reg_sec);
1023 if (pvt->umc)
1069 if (pvt->umc) {
1070 if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5))
1072 else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4))
1459 channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT);
1593 static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,
1621 addr_mask_orig = pvt->csels[umc].csmasks_sec[dimm];
1623 addr_mask_orig = pvt->csels[umc].csmasks[dimm];
2693 if (pvt->umc) {
2748 if (pvt->umc) {
2761 if (pvt->umc) {
2766 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
2767 if (pvt->umc[i].ecc_ctrl & BIT(9)) {
2770 } else if (pvt->umc[i].ecc_ctrl & BIT(7)) {
2796 struct amd64_umc *umc;
2803 umc = &pvt->umc[i];
2805 amd_smn_read(nid, umc_base + UMCCH_DIMM_CFG, &umc->dimm_cfg);
2806 amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg);
2807 amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl);
2808 amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl);
2809 amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi);
2838 if (pvt->umc) {
2934 if (!pvt->umc) {
2958 u8 umc, cs;
2973 for_each_umc(umc) {
2974 for_each_chip_select(cs, umc, pvt) {
2975 if (!csrow_enabled(cs, umc, pvt))
2979 dimm = mci->csrows[cs]->channels[umc]->dimm;
2984 dimm->nr_pages = get_csrow_nr_pages(pvt, umc, cs);
3009 if (pvt->umc)
3241 struct amd64_umc *umc;
3244 umc = &pvt->umc[i];
3247 if (!(umc->sdp_ctrl & UMC_SDP_INIT))
3252 if (umc->umc_cap_hi & UMC_ECC_ENABLED)
3290 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
3291 ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED);
3292 cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP);
3294 dev_x4 &= !!(pvt->umc[i].dimm_cfg & BIT(6));
3295 dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7));
3322 if (pvt->umc) {
3460 pvt->umc = kcalloc(fam_type->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL);
3461 if (!pvt->umc)
3485 kfree(pvt->umc);