Lines Matching refs:range
366 "range for node %d with node interleaving enabled.\n",
573 * Limit registers for node n. If the SysAddr is not within the range
579 * the range of relocated addresses (starting at 0x100000000) from the DRAM
1234 static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
1239 int off = range << 3;
1242 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo);
1243 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo);
1248 if (!dram_rw(pvt, range))
1251 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi);
1252 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);
1258 nb = node_to_amd_nb(dram_dst_node(pvt, range));
1275 pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0);
1278 pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
1280 pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0);
1283 pvt->ranges[range].lim.hi |= llim >> 13;
1661 edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",
1668 edac_dbg(0, " Address range split per DCT: %s\n",
1763 static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range,
1768 u64 dram_base = get_dram_base(pvt, range);
1775 * base address of high range is below 4Gb
1782 * remove high range offset from sys_addr
1918 static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
1927 u8 node_id = dram_dst_node(pvt, range);
1928 u8 intlv_en = dram_intlv_en(pvt, range);
1929 u32 intlv_sel = dram_intlv_sel(pvt, range);
1931 edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
1932 range, sys_addr, get_dram_limit(pvt, range));
1960 chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr,
1998 static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
2010 u8 node_id = dram_dst_node(pvt, range);
2011 u8 intlv_en = dram_intlv_en(pvt, range);
2019 edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
2020 range, sys_addr, get_dram_limit(pvt, range));
2022 if (!(get_dram_base(pvt, range) <= sys_addr) &&
2023 !(get_dram_limit(pvt, range) >= sys_addr))
2125 unsigned range;
2127 for (range = 0; range < DRAM_RANGES; range++) {
2128 if (!dram_rw(pvt, range))
2132 cs_found = f15_m30h_match_to_this_node(pvt, range,
2136 else if ((get_dram_base(pvt, range) <= sys_addr) &&
2137 (get_dram_limit(pvt, range) >= sys_addr)) {
2138 cs_found = f1x_match_to_this_node(pvt, range,
2819 unsigned int range;
2849 for (range = 0; range < DRAM_RANGES; range++) {
2852 /* read settings for this DRAM range */
2853 read_dram_base_limit_regs(pvt, range);
2855 rw = dram_rw(pvt, range);
2859 edac_dbg(1, " DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",
2860 range,
2861 get_dram_base(pvt, range),
2862 get_dram_limit(pvt, range));
2865 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled",
2868 dram_intlv_sel(pvt, range),
2869 dram_dst_node(pvt, range));
2912 * Values range from: 0 to 15