Lines Matching refs:cs_mode
797 int cs_mode = 0;
800 cs_mode |= CS_EVEN_PRIMARY;
803 cs_mode |= CS_ODD_PRIMARY;
807 cs_mode |= CS_ODD_SECONDARY;
820 cs_mode |= CS_3R_INTERLEAVE;
823 return cs_mode;
828 int dimm, size0, size1, cs0, cs1, cs_mode;
836 cs_mode = f17_get_cs_mode(dimm, ctrl, pvt);
838 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs0);
839 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs1);
1357 unsigned cs_mode, int cs_mask_nr)
1362 WARN_ON(cs_mode > 11);
1363 return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
1367 WARN_ON(cs_mode > 10);
1371 * contest, maps cs_mode values to DIMM chip select sizes. The
1374 * cs_mode CS size (mb)
1393 diff = cs_mode/3 + (unsigned)(cs_mode > 5);
1395 return 32 << (cs_mode - diff);
1398 WARN_ON(cs_mode > 6);
1399 return 32 << cs_mode;
1524 unsigned cs_mode, int cs_mask_nr)
1528 WARN_ON(cs_mode > 11);
1531 return ddr3_cs_size(cs_mode, dclr & WIDTH_128);
1533 return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
1540 unsigned cs_mode, int cs_mask_nr)
1542 WARN_ON(cs_mode > 12);
1544 return ddr3_cs_size(cs_mode, false);
1549 unsigned cs_mode, int cs_mask_nr)
1554 WARN_ON(cs_mode > 12);
1557 if (cs_mode > 9)
1560 cs_size = ddr4_cs_size(cs_mode);
1566 cs_size = ddr3_lrdimm_cs_size(cs_mode, rank_multiply);
1569 if (cs_mode == 0x1)
1572 cs_size = ddr3_cs_size(cs_mode, false);
1582 unsigned cs_mode, int cs_mask_nr)
1584 WARN_ON(cs_mode > 12);
1586 if (cs_mode == 6 || cs_mode == 8 ||
1587 cs_mode == 9 || cs_mode == 12)
1590 return ddr3_cs_size(cs_mode, false);
1594 unsigned int cs_mode, int csrow_nr)
1601 if (!cs_mode)
1605 if (!(cs_mode & CS_EVEN) && !(csrow_nr & 1))
1609 if (!(cs_mode & CS_ODD) && (csrow_nr & 1))
1620 if ((csrow_nr & 1) && (cs_mode & CS_ODD_SECONDARY))
1638 num_zero_bits = msb - weight - !!(cs_mode & CS_3R_INTERLEAVE);
2932 u32 cs_mode, nr_pages;
2936 cs_mode = DBAM_DIMM(csrow_nr, dbam);
2938 cs_mode = f17_get_cs_mode(csrow_nr >> 1, dct, pvt);
2941 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr);
2945 csrow_nr_orig, dct, cs_mode);