Lines Matching defs:dct
89 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct)
95 reg |= dct;
113 static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct,
118 if (dct || offset >= 0x100)
123 if (dct) {
141 dct = (dct && pvt->model == 0x30) ? 3 : dct;
142 f15h_select_dct(pvt, dct);
146 if (dct)
382 * compute the CS base address of the @csrow on the DRAM controller @dct.
385 static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct,
392 csbase = pvt->csels[dct].csbases[csrow];
393 csmask = pvt->csels[dct].csmasks[csrow];
404 csbase = pvt->csels[dct].csbases[csrow];
405 csmask = pvt->csels[dct].csmasks[csrow >> 1];
420 csbase = pvt->csels[dct].csbases[csrow];
421 csmask = pvt->csels[dct].csmasks[csrow >> 1];
441 #define for_each_chip_select(i, dct, pvt) \
442 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
444 #define chip_select_base(i, dct, pvt) \
445 pvt->csels[dct].csbases[i]
447 #define for_each_chip_select_mask(i, dct, pvt) \
448 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
1356 static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1359 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
1523 static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1526 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
1539 static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1548 static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1552 u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr];
1581 static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1814 static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow)
1818 if (online_spare_swap_done(pvt, dct) &&
1819 csrow == online_spare_bad_dramcs(pvt, dct)) {
1821 for_each_chip_select(tmp_cs, dct, pvt) {
1822 if (chip_select_base(tmp_cs, dct, pvt) & 0x2) {
1839 static int f1x_lookup_addr_in_dct(u64 in_addr, u8 nid, u8 dct)
1853 edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct);
1855 for_each_chip_select(csrow, dct, pvt) {
1856 if (!csrow_enabled(csrow, dct, pvt))
1859 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask);
1874 cs_found = f10_process_possible_spare(pvt, dct, csrow);
2043 /* Verify number of dct's that participate in channel interleaving. */
2928 static u32 get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig)
2930 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0;
2938 cs_mode = f17_get_cs_mode(csrow_nr >> 1, dct, pvt);
2941 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr);
2945 csrow_nr_orig, dct, cs_mode);
3542 int cs = 0, dct = 0;
3544 for (dct = 0; dct < fam_type->max_mcs; dct++) {
3545 for_each_chip_select(cs, dct, pvt)
3546 cs_enabled |= csrow_enabled(cs, dct, pvt);