Lines Matching refs:reg
210 * @reg: register base address
226 void __iomem *reg;
252 * @reg: register base address
261 void __iomem *reg;
753 u32 reg;
755 reg = (XILINX_DPDMA_INTR_CHAN_MASK << chan->id)
757 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg);
758 reg = (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id)
760 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg);
762 reg = XILINX_DPDMA_CH_CNTL_ENABLE
769 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, reg);
780 u32 reg;
782 reg = XILINX_DPDMA_INTR_CHAN_MASK << chan->id;
783 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg);
784 reg = XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id;
785 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg);
787 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE);
798 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE);
809 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE);
842 u32 reg, channels;
875 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR,
878 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE,
898 reg = XILINX_DPDMA_GBL_TRIG_MASK(channels);
900 reg = XILINX_DPDMA_GBL_RETRIG_MASK(channels);
902 dpdma_write(xdev->reg, XILINX_DPDMA_GBL, reg);
916 dpdma_read(chan->reg, XILINX_DPDMA_CH_STATUS));
944 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IDS,
970 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN,
1005 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN,
1091 desc_id = dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_ID)
1155 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE),
1156 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR));
1158 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDRE),
1159 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDR));
1435 dpdma_write(xdev->reg, XILINX_DPDMA_IDS,
1437 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS,
1453 dpdma_write(xdev->reg, XILINX_DPDMA_IEN, XILINX_DPDMA_INTR_ALL);
1454 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN, XILINX_DPDMA_EINTR_ALL);
1465 dpdma_write(xdev->reg, XILINX_DPDMA_IDS, XILINX_DPDMA_INTR_ALL);
1466 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS, XILINX_DPDMA_EINTR_ALL);
1488 dpdma_write(xdev->reg, XILINX_DPDMA_IEN,
1490 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN,
1506 status = dpdma_read(xdev->reg, XILINX_DPDMA_ISR);
1507 error = dpdma_read(xdev->reg, XILINX_DPDMA_EISR);
1511 dpdma_write(xdev->reg, XILINX_DPDMA_ISR, status);
1512 dpdma_write(xdev->reg, XILINX_DPDMA_EISR, error);
1560 chan->reg = xdev->reg + XILINX_DPDMA_CH_BASE
1605 void __iomem *reg;
1612 reg = xdev->reg + XILINX_DPDMA_CH_BASE
1614 dpdma_clr(reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE);
1618 dpdma_write(xdev->reg, XILINX_DPDMA_ISR, XILINX_DPDMA_INTR_ALL);
1619 dpdma_write(xdev->reg, XILINX_DPDMA_EISR, XILINX_DPDMA_EINTR_ALL);
1644 xdev->reg = devm_platform_ioremap_resource(pdev, 0);
1645 if (IS_ERR(xdev->reg))
1646 return PTR_ERR(xdev->reg);