Lines Matching defs:sw_desc
506 * @sw_desc: The software descriptor in which to set DMA addresses
513 * descriptor DMA address is set to the DMA address of @sw_desc. @prev may be
514 * identical to @sw_desc for cyclic transfers.
517 struct xilinx_dpdma_sw_desc *sw_desc,
522 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
549 prev->hw.next_desc = lower_32_bits(sw_desc->dma_addr);
553 upper_32_bits(sw_desc->dma_addr));
567 struct xilinx_dpdma_sw_desc *sw_desc;
570 sw_desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &dma_addr);
571 if (!sw_desc)
574 sw_desc->dma_addr = dma_addr;
576 return sw_desc;
582 * @sw_desc: software descriptor to free
588 struct xilinx_dpdma_sw_desc *sw_desc)
590 dma_pool_free(chan->desc_pool, sw_desc, sw_desc->dma_addr);
603 struct xilinx_dpdma_sw_desc *sw_desc;
610 list_for_each_entry(sw_desc, &tx_desc->descriptors, node) {
611 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
614 dev_dbg(dev, "descriptor DMA addr: %pad\n", &sw_desc->dma_addr);
668 struct xilinx_dpdma_sw_desc *sw_desc, *next;
676 list_for_each_entry_safe(sw_desc, next, &desc->descriptors, node) {
677 list_del(&sw_desc->node);
678 xilinx_dpdma_chan_free_sw_desc(desc->chan, sw_desc);
700 struct xilinx_dpdma_sw_desc *sw_desc;
715 sw_desc = xilinx_dpdma_chan_alloc_sw_desc(chan);
716 if (!sw_desc) {
721 xilinx_dpdma_sw_desc_set_dma_addrs(chan->xdev, sw_desc, sw_desc,
724 hw_desc = &sw_desc->hw;
736 list_add_tail(&sw_desc->node, &tx_desc->descriptors);
839 struct xilinx_dpdma_sw_desc *sw_desc;
869 list_for_each_entry(sw_desc, &desc->descriptors, node)
870 sw_desc->hw.desc_id = desc->vdesc.tx.cookie
873 sw_desc = list_first_entry(&desc->descriptors,
876 lower_32_bits(sw_desc->dma_addr));
880 upper_32_bits(sw_desc->dma_addr)));
1081 struct xilinx_dpdma_sw_desc *sw_desc;
1095 sw_desc = list_first_entry(&pending->descriptors,
1097 if (sw_desc->hw.desc_id != desc_id)