Lines Matching defs:val
521 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \
523 val, cond, delay_us, timeout_us)
1279 u32 val;
1284 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1285 val & XILINX_DMA_DMASR_HALTED, 0,
1297 u32 val;
1299 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1300 val & XILINX_DMA_DMASR_IDLE, 0,
1311 u32 val;
1316 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1317 !(val & XILINX_DMA_DMASR_HALTED), 0,