Lines Matching refs:pdma
215 struct xgene_dma *pdma;
247 * @pdma: X-Gene DMA device structure reference
271 struct xgene_dma *pdma;
343 static bool is_pq_enabled(struct xgene_dma *pdma)
347 val = ioread32(pdma->csr_efuse + XGENE_SOC_JTAG1_SHADOW);
1013 struct xgene_dma *pdma = (struct xgene_dma *)id;
1017 val = ioread32(pdma->csr_dma + XGENE_DMA_INT);
1020 iowrite32(val, pdma->csr_dma + XGENE_DMA_INT);
1025 dev_err(pdma->dev,
1035 iowrite32(ring->num, ring->pdma->csr_ring + XGENE_DMA_RING_STATE);
1038 iowrite32(ring->state[i], ring->pdma->csr_ring +
1082 ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1086 ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1100 val = ioread32(ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1102 iowrite32(val, ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1111 val = ioread32(ring->pdma->csr_ring +
1114 iowrite32(val, ring->pdma->csr_ring +
1120 iowrite32(ring_id, ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1122 iowrite32(0, ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1128 ring->cmd_base = ring->pdma->csr_ring_cmd +
1171 dma_free_coherent(ring->pdma->dev, ring->size,
1190 ring->pdma = chan->pdma;
1192 ring->num = chan->pdma->ring_num++;
1256 static int xgene_dma_init_rings(struct xgene_dma *pdma)
1261 ret = xgene_dma_create_chan_rings(&pdma->chan[i]);
1264 xgene_dma_delete_chan_rings(&pdma->chan[j]);
1272 static void xgene_dma_enable(struct xgene_dma *pdma)
1277 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1280 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1283 static void xgene_dma_disable(struct xgene_dma *pdma)
1287 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1289 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1292 static void xgene_dma_mask_interrupts(struct xgene_dma *pdma)
1299 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1301 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1303 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1305 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1307 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1310 iowrite32(XGENE_DMA_INT_ALL_MASK, pdma->csr_dma + XGENE_DMA_INT_MASK);
1313 static void xgene_dma_unmask_interrupts(struct xgene_dma *pdma)
1320 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1322 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1324 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1326 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1328 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1332 pdma->csr_dma + XGENE_DMA_INT_MASK);
1335 static void xgene_dma_init_hw(struct xgene_dma *pdma)
1341 pdma->csr_dma + XGENE_DMA_CFG_RING_WQ_ASSOC);
1344 if (is_pq_enabled(pdma))
1346 pdma->csr_dma + XGENE_DMA_RAID6_CONT);
1348 dev_info(pdma->dev, "PQ is disabled in HW\n");
1350 xgene_dma_enable(pdma);
1351 xgene_dma_unmask_interrupts(pdma);
1354 val = ioread32(pdma->csr_dma + XGENE_DMA_IPBRR);
1357 dev_info(pdma->dev,
1363 static int xgene_dma_init_ring_mngr(struct xgene_dma *pdma)
1365 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_CLKEN) &&
1366 (!ioread32(pdma->csr_ring + XGENE_DMA_RING_SRST)))
1369 iowrite32(0x3, pdma->csr_ring + XGENE_DMA_RING_CLKEN);
1370 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_SRST);
1373 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1376 ioread32(pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1381 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_BLK_MEM_RDY)
1383 dev_err(pdma->dev,
1390 pdma->csr_ring + XGENE_DMA_RING_THRESLD0_SET1);
1392 pdma->csr_ring + XGENE_DMA_RING_THRESLD1_SET1);
1394 pdma->csr_ring + XGENE_DMA_RING_HYSTERESIS);
1398 pdma->csr_ring + XGENE_DMA_RING_CONFIG);
1403 static int xgene_dma_init_mem(struct xgene_dma *pdma)
1407 ret = xgene_dma_init_ring_mngr(pdma);
1412 iowrite32(0x0, pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1415 ioread32(pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1420 if (ioread32(pdma->csr_dma + XGENE_DMA_BLK_MEM_RDY)
1422 dev_err(pdma->dev,
1430 static int xgene_dma_request_irqs(struct xgene_dma *pdma)
1436 ret = devm_request_irq(pdma->dev, pdma->err_irq, xgene_dma_err_isr,
1437 0, "dma_error", pdma);
1439 dev_err(pdma->dev,
1440 "Failed to register error IRQ %d\n", pdma->err_irq);
1446 chan = &pdma->chan[i];
1454 devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1457 chan = &pdma->chan[i];
1469 static void xgene_dma_free_irqs(struct xgene_dma *pdma)
1475 devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1478 chan = &pdma->chan[i];
1502 is_pq_enabled(chan->pdma)) {
1506 !is_pq_enabled(chan->pdma)) {
1530 static int xgene_dma_async_register(struct xgene_dma *pdma, int id)
1532 struct xgene_dma_chan *chan = &pdma->chan[id];
1533 struct dma_device *dma_dev = &pdma->dma_dev[id];
1565 dev_info(pdma->dev,
1573 static int xgene_dma_init_async(struct xgene_dma *pdma)
1578 ret = xgene_dma_async_register(pdma, i);
1581 dma_async_device_unregister(&pdma->dma_dev[j]);
1582 tasklet_kill(&pdma->chan[j].tasklet);
1592 static void xgene_dma_async_unregister(struct xgene_dma *pdma)
1597 dma_async_device_unregister(&pdma->dma_dev[i]);
1600 static void xgene_dma_init_channels(struct xgene_dma *pdma)
1605 pdma->ring_num = XGENE_DMA_RING_NUM;
1608 chan = &pdma->chan[i];
1609 chan->dev = pdma->dev;
1610 chan->pdma = pdma;
1617 struct xgene_dma *pdma)
1629 pdma->csr_dma = devm_ioremap(&pdev->dev, res->start,
1631 if (!pdma->csr_dma) {
1643 pdma->csr_ring = devm_ioremap(&pdev->dev, res->start,
1645 if (!pdma->csr_ring) {
1657 pdma->csr_ring_cmd = devm_ioremap(&pdev->dev, res->start,
1659 if (!pdma->csr_ring_cmd) {
1664 pdma->csr_ring_cmd += XGENE_DMA_RING_CMD_SM_OFFSET;
1673 pdma->csr_efuse = devm_ioremap(&pdev->dev, res->start,
1675 if (!pdma->csr_efuse) {
1685 pdma->err_irq = irq;
1693 pdma->chan[i - 1].rx_irq = irq;
1701 struct xgene_dma *pdma;
1704 pdma = devm_kzalloc(&pdev->dev, sizeof(*pdma), GFP_KERNEL);
1705 if (!pdma)
1708 pdma->dev = &pdev->dev;
1709 platform_set_drvdata(pdev, pdma);
1711 ret = xgene_dma_get_resources(pdev, pdma);
1715 pdma->clk = devm_clk_get(&pdev->dev, NULL);
1716 if (IS_ERR(pdma->clk) && !ACPI_COMPANION(&pdev->dev)) {
1718 return PTR_ERR(pdma->clk);
1722 if (!IS_ERR(pdma->clk)) {
1723 ret = clk_prepare_enable(pdma->clk);
1731 ret = xgene_dma_init_mem(pdma);
1742 xgene_dma_init_channels(pdma);
1745 ret = xgene_dma_init_rings(pdma);
1749 ret = xgene_dma_request_irqs(pdma);
1754 xgene_dma_init_hw(pdma);
1757 ret = xgene_dma_init_async(pdma);
1764 xgene_dma_free_irqs(pdma);
1768 xgene_dma_delete_chan_rings(&pdma->chan[i]);
1772 if (!IS_ERR(pdma->clk))
1773 clk_disable_unprepare(pdma->clk);
1780 struct xgene_dma *pdma = platform_get_drvdata(pdev);
1784 xgene_dma_async_unregister(pdma);
1787 xgene_dma_mask_interrupts(pdma);
1788 xgene_dma_disable(pdma);
1789 xgene_dma_free_irqs(pdma);
1792 chan = &pdma->chan[i];
1797 if (!IS_ERR(pdma->clk))
1798 clk_disable_unprepare(pdma->clk);