Lines Matching refs:csr_dma
294 * @csr_dma: base for DMA register access
306 void __iomem *csr_dma;
1017 val = ioread32(pdma->csr_dma + XGENE_DMA_INT);
1020 iowrite32(val, pdma->csr_dma + XGENE_DMA_INT);
1277 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1280 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1287 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1289 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1299 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1301 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1303 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1305 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1307 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1310 iowrite32(XGENE_DMA_INT_ALL_MASK, pdma->csr_dma + XGENE_DMA_INT_MASK);
1320 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1322 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1324 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1326 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1328 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1332 pdma->csr_dma + XGENE_DMA_INT_MASK);
1341 pdma->csr_dma + XGENE_DMA_CFG_RING_WQ_ASSOC);
1346 pdma->csr_dma + XGENE_DMA_RAID6_CONT);
1354 val = ioread32(pdma->csr_dma + XGENE_DMA_IPBRR);
1412 iowrite32(0x0, pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1415 ioread32(pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1420 if (ioread32(pdma->csr_dma + XGENE_DMA_BLK_MEM_RDY)
1629 pdma->csr_dma = devm_ioremap(&pdev->dev, res->start,
1631 if (!pdma->csr_dma) {