Lines Matching refs:ucc
747 struct udma_chan_config *ucc = &uc->config;
749 if (ucc->pkt_mode && (uc->cyclic || ucc->dir == DMA_DEV_TO_MEM)) {
3006 struct udma_chan_config *ucc;
3016 ucc = &uc->config;
3026 ucc->remote_thread_id = filter_param->remote_thread_id;
3027 ucc->atype = filter_param->atype;
3029 if (ucc->remote_thread_id & K3_PSIL_DST_THREAD_ID_OFFSET)
3030 ucc->dir = DMA_MEM_TO_DEV;
3032 ucc->dir = DMA_DEV_TO_MEM;
3034 ep_config = psil_get_ep_config(ucc->remote_thread_id);
3037 ucc->remote_thread_id);
3038 ucc->dir = DMA_MEM_TO_MEM;
3039 ucc->remote_thread_id = -1;
3040 ucc->atype = 0;
3044 ucc->pkt_mode = ep_config->pkt_mode;
3045 ucc->channel_tpl = ep_config->channel_tpl;
3046 ucc->notdpkt = ep_config->notdpkt;
3047 ucc->ep_type = ep_config->ep_type;
3049 if (ucc->ep_type != PSIL_EP_NATIVE) {
3053 ucc->enable_acc32 = ep_config->pdma_acc32;
3055 ucc->enable_burst = ep_config->pdma_burst;
3058 ucc->needs_epib = ep_config->needs_epib;
3059 ucc->psd_size = ep_config->psd_size;
3060 ucc->metadata_size =
3061 (ucc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) +
3062 ucc->psd_size;
3064 if (ucc->pkt_mode)
3065 ucc->hdesc_size = ALIGN(sizeof(struct cppi5_host_desc_t) +
3066 ucc->metadata_size, ud->desc_align);
3069 ucc->remote_thread_id, dmaengine_get_direction_text(ucc->dir));
3448 struct udma_chan_config *ucc = &uc->config;
3457 ucc->src_thread, ucc->dst_thread);
3461 ucc->src_thread, ucc->dst_thread);
3465 ucc->src_thread, ucc->dst_thread);
3472 if (ucc->ep_type == PSIL_EP_NATIVE) {
3474 if (ucc->metadata_size) {
3475 seq_printf(s, "[%s", ucc->needs_epib ? " EPIB" : "");
3476 if (ucc->psd_size)
3477 seq_printf(s, " PSDsize:%u", ucc->psd_size);
3482 if (ucc->enable_acc32 || ucc->enable_burst)
3484 ucc->enable_acc32 ? " ACC32" : "",
3485 ucc->enable_burst ? " BURST" : "");
3488 seq_printf(s, ", %s)\n", ucc->pkt_mode ? "Packet mode" : "TR mode");