Lines Matching refs:tr_req
2025 struct cppi5_tr_type1_t *tr_req = NULL;
2048 tr_req = d->hwdesc[0].tr_req_base;
2062 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false,
2064 cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT);
2066 tr_req[tr_idx].addr = sg_addr;
2067 tr_req[tr_idx].icnt0 = tr0_cnt0;
2068 tr_req[tr_idx].icnt1 = tr0_cnt1;
2069 tr_req[tr_idx].dim1 = tr0_cnt0;
2073 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1,
2076 cppi5_tr_csf_set(&tr_req[tr_idx].flags,
2079 tr_req[tr_idx].addr = sg_addr + tr0_cnt1 * tr0_cnt0;
2080 tr_req[tr_idx].icnt0 = tr1_cnt0;
2081 tr_req[tr_idx].icnt1 = 1;
2082 tr_req[tr_idx].dim1 = tr1_cnt0;
2089 cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags,
2397 struct cppi5_tr_type1_t *tr_req;
2417 tr_req = d->hwdesc[0].tr_req_base;
2422 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false,
2425 tr_req[tr_idx].addr = period_addr;
2426 tr_req[tr_idx].icnt0 = tr0_cnt0;
2427 tr_req[tr_idx].icnt1 = tr0_cnt1;
2428 tr_req[tr_idx].dim1 = tr0_cnt0;
2431 cppi5_tr_csf_set(&tr_req[tr_idx].flags,
2435 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1,
2439 tr_req[tr_idx].addr = period_addr + tr0_cnt1 * tr0_cnt0;
2440 tr_req[tr_idx].icnt0 = tr1_cnt0;
2441 tr_req[tr_idx].icnt1 = 1;
2442 tr_req[tr_idx].dim1 = tr1_cnt0;
2446 cppi5_tr_csf_set(&tr_req[tr_idx].flags,
2593 struct cppi5_tr_type15_t *tr_req;
2624 tr_req = d->hwdesc[0].tr_req_base;
2626 cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true,
2628 cppi5_tr_csf_set(&tr_req[0].flags, CPPI5_TR_CSF_SUPR_EVT);
2630 tr_req[0].addr = src;
2631 tr_req[0].icnt0 = tr0_cnt0;
2632 tr_req[0].icnt1 = tr0_cnt1;
2633 tr_req[0].icnt2 = 1;
2634 tr_req[0].icnt3 = 1;
2635 tr_req[0].dim1 = tr0_cnt0;
2637 tr_req[0].daddr = dest;
2638 tr_req[0].dicnt0 = tr0_cnt0;
2639 tr_req[0].dicnt1 = tr0_cnt1;
2640 tr_req[0].dicnt2 = 1;
2641 tr_req[0].dicnt3 = 1;
2642 tr_req[0].ddim1 = tr0_cnt0;
2645 cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true,
2647 cppi5_tr_csf_set(&tr_req[1].flags, CPPI5_TR_CSF_SUPR_EVT);
2649 tr_req[1].addr = src + tr0_cnt1 * tr0_cnt0;
2650 tr_req[1].icnt0 = tr1_cnt0;
2651 tr_req[1].icnt1 = 1;
2652 tr_req[1].icnt2 = 1;
2653 tr_req[1].icnt3 = 1;
2655 tr_req[1].daddr = dest + tr0_cnt1 * tr0_cnt0;
2656 tr_req[1].dicnt0 = tr1_cnt0;
2657 tr_req[1].dicnt1 = 1;
2658 tr_req[1].dicnt2 = 1;
2659 tr_req[1].dicnt3 = 1;
2662 cppi5_tr_csf_set(&tr_req[num_tr - 1].flags,
3352 struct cppi5_tr_type1_t *tr_req;
3399 tr_req = hwdesc->tr_req_base;
3400 cppi5_tr_init(&tr_req->flags, CPPI5_TR_TYPE1, false, false,
3402 cppi5_tr_csf_set(&tr_req->flags, CPPI5_TR_CSF_SUPR_EVT);
3404 tr_req->addr = rx_flush->buffer_paddr;
3405 tr_req->icnt0 = rx_flush->buffer_size;
3406 tr_req->icnt1 = 1;