Lines Matching defs:ret
592 int ret;
606 ret = k3_ringacc_ring_pop(ring, addr);
607 if (ret)
608 return ret;
719 int ret;
726 ret = uc->ud->ddev.device_alloc_chan_resources(&uc->vc.chan);
727 if (ret)
728 return ret;
1382 int ret;
1384 ret = udma_get_tchan(uc);
1385 if (ret)
1386 return ret;
1388 ret = k3_ringacc_request_rings_pair(ud->ringacc, uc->tchan->id, -1,
1391 if (ret) {
1392 ret = -EBUSY;
1401 ret = k3_ringacc_ring_cfg(uc->tchan->t_ring, &ring_cfg);
1402 ret |= k3_ringacc_ring_cfg(uc->tchan->tc_ring, &ring_cfg);
1404 if (ret)
1417 return ret;
1445 int ret;
1447 ret = udma_get_rchan(uc);
1448 if (ret)
1449 return ret;
1455 ret = udma_get_rflow(uc, uc->rchan->id);
1456 if (ret) {
1457 ret = -EBUSY;
1463 ret = k3_ringacc_request_rings_pair(ud->ringacc, fd_ring_id, -1,
1465 if (ret) {
1466 ret = -EBUSY;
1480 ret = k3_ringacc_ring_cfg(rflow->fd_ring, &ring_cfg);
1482 ret |= k3_ringacc_ring_cfg(rflow->r_ring, &ring_cfg);
1484 if (ret)
1499 return ret;
1530 int ret = 0;
1545 ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx);
1546 if (ret) {
1547 dev_err(ud->dev, "tchan%d cfg failed %d\n", tchan->id, ret);
1548 return ret;
1559 ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx);
1560 if (ret)
1561 dev_err(ud->dev, "rchan%d alloc failed %d\n", rchan->id, ret);
1563 return ret;
1575 int ret = 0;
1595 ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx);
1596 if (ret)
1597 dev_err(ud->dev, "tchan%d cfg failed %d\n", tchan->id, ret);
1599 return ret;
1613 int ret = 0;
1632 ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx);
1633 if (ret) {
1634 dev_err(ud->dev, "rchan%d cfg failed %d\n", rchan->id, ret);
1635 return ret;
1675 ret = tisci_ops->rx_flow_cfg(tisci_rm->tisci, &flow_req);
1677 if (ret)
1678 dev_err(ud->dev, "flow%d config failed: %d\n", rchan->id, ret);
1690 int ret;
1711 ret = -ENOMEM;
1730 ret = udma_get_chan_pair(uc);
1731 if (ret)
1734 ret = udma_alloc_tx_resources(uc);
1735 if (ret) {
1740 ret = udma_alloc_rx_resources(uc);
1741 if (ret) {
1753 ret = udma_tisci_m2m_channel_config(uc);
1760 ret = udma_alloc_tx_resources(uc);
1761 if (ret)
1771 ret = udma_tisci_tx_channel_config(uc);
1778 ret = udma_alloc_rx_resources(uc);
1779 if (ret)
1789 ret = udma_tisci_rx_channel_config(uc);
1795 ret = -EINVAL;
1801 if (ret)
1809 ret = -EBUSY;
1815 ret = navss_psil_pair(ud, uc->config.src_thread, uc->config.dst_thread);
1816 if (ret) {
1828 ret = -EINVAL;
1832 ret = request_irq(uc->irq_num_ring, udma_ring_irq_handler,
1834 if (ret) {
1847 ret = -EINVAL;
1851 ret = request_irq(uc->irq_num_udma, udma_udma_irq_handler, 0,
1853 if (ret) {
1884 return ret;
2698 enum dma_status ret;
2703 ret = dma_cookie_status(chan, cookie, txstate);
2706 ret = DMA_COMPLETE;
2708 if (ret == DMA_IN_PROGRESS && udma_is_chan_paused(uc))
2709 ret = DMA_PAUSED;
2711 if (ret == DMA_COMPLETE || !txstate)
2751 ret = DMA_COMPLETE;
2759 ret = DMA_COMPLETE;
2764 return ret;
3180 int ch_count, ret, i, j;
3305 ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res);
3307 if (ret) {
3309 return ret;
3516 int i, ret;
3519 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(48));
3520 if (ret)
3527 ret = udma_get_mmrs(pdev, ud);
3528 if (ret)
3529 return ret;
3535 ret = of_property_read_u32(dev->of_node, "ti,sci-dev-id",
3537 if (ret) {
3538 dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
3539 return ret;
3543 ret = of_property_read_u32(navss_node, "ti,sci-dev-id",
3545 if (ret) {
3546 dev_err(dev, "NAVSS ti,sci-dev-id read failure %d\n", ret);
3547 return ret;
3550 ret = of_property_read_u32(dev->of_node, "ti,udma-atype", &ud->atype);
3551 if (!ret && ud->atype > 2) {
3633 ret = udma_setup_rx_flush(ud);
3634 if (ret)
3635 return ret;
3677 ret = dma_async_device_register(&ud->ddev);
3678 if (ret) {
3679 dev_err(dev, "failed to register slave DMA engine: %d\n", ret);
3680 return ret;
3685 ret = of_dma_controller_register(dev->of_node, udma_of_xlate, ud);
3686 if (ret) {
3691 return ret;