Lines Matching defs:ddev
120 struct dma_device ddev;
252 return container_of(d, struct udma_dev, ddev);
722 uc->ud->ddev.device_free_chan_resources(&uc->vc.chan);
726 ret = uc->ud->ddev.device_alloc_chan_resources(&uc->vc.chan);
1703 uc->hdesc_pool = dma_pool_create(uc->name, ud->ddev.dev,
1708 dev_err(ud->ddev.dev,
3078 dma_cap_mask_t mask = ud->ddev.cap_mask;
3584 dma_cap_set(DMA_SLAVE, ud->ddev.cap_mask);
3585 dma_cap_set(DMA_CYCLIC, ud->ddev.cap_mask);
3587 ud->ddev.device_alloc_chan_resources = udma_alloc_chan_resources;
3588 ud->ddev.device_config = udma_slave_config;
3589 ud->ddev.device_prep_slave_sg = udma_prep_slave_sg;
3590 ud->ddev.device_prep_dma_cyclic = udma_prep_dma_cyclic;
3591 ud->ddev.device_issue_pending = udma_issue_pending;
3592 ud->ddev.device_tx_status = udma_tx_status;
3593 ud->ddev.device_pause = udma_pause;
3594 ud->ddev.device_resume = udma_resume;
3595 ud->ddev.device_terminate_all = udma_terminate_all;
3596 ud->ddev.device_synchronize = udma_synchronize;
3598 ud->ddev.dbg_summary_show = udma_dbg_summary_show;
3601 ud->ddev.device_free_chan_resources = udma_free_chan_resources;
3602 ud->ddev.src_addr_widths = TI_UDMAC_BUSWIDTHS;
3603 ud->ddev.dst_addr_widths = TI_UDMAC_BUSWIDTHS;
3604 ud->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
3605 ud->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
3606 ud->ddev.copy_align = DMAENGINE_ALIGN_8_BYTES;
3607 ud->ddev.desc_metadata_modes = DESC_METADATA_CLIENT |
3610 dma_cap_set(DMA_MEMCPY, ud->ddev.cap_mask);
3611 ud->ddev.device_prep_dma_memcpy = udma_prep_dma_memcpy;
3612 ud->ddev.directions |= BIT(DMA_MEM_TO_MEM);
3615 ud->ddev.dev = dev;
3619 INIT_LIST_HEAD(&ud->ddev.channels);
3670 vchan_init(&uc->vc, &ud->ddev);
3677 ret = dma_async_device_register(&ud->ddev);
3688 dma_async_device_unregister(&ud->ddev);