Lines Matching defs:config
241 struct udma_chan_config config;
358 memset(&uc->config, 0, sizeof(uc->config));
359 uc->config.remote_thread_id = -1;
369 if (uc->config.dir == DMA_MEM_TO_DEV || uc->config.dir == DMA_MEM_TO_MEM) {
378 if (uc->config.dir == DMA_DEV_TO_MEM || uc->config.dir == DMA_MEM_TO_MEM) {
520 switch (uc->config.dir) {
545 return uc->ud->rx_flush.hwdescs[uc->config.pkt_mode].cppi5_desc_paddr;
554 switch (uc->config.dir) {
580 if (uc->config.dir != DMA_DEV_TO_MEM)
594 switch (uc->config.dir) {
628 switch (uc->config.dir) {
696 switch (uc->config.dir) {
721 memcpy(&ucc_backup, &uc->config, sizeof(uc->config));
725 memcpy(&uc->config, &ucc_backup, sizeof(uc->config));
734 if (uc->config.dir == DMA_DEV_TO_MEM)
747 struct udma_chan_config *ucc = &uc->config;
763 if (uc->config.ep_type == PSIL_EP_NATIVE)
801 if (uc->config.ep_type == PSIL_EP_PDMA_XY) {
807 if (uc->config.enable_acc32)
809 if (uc->config.enable_burst)
836 if (uc->config.ep_type == PSIL_EP_PDMA_XY) {
840 if (uc->config.enable_acc32)
842 if (uc->config.enable_burst)
886 switch (uc->config.dir) {
940 if (uc->config.ep_type == PSIL_EP_NATIVE ||
941 uc->config.dir != DMA_MEM_TO_DEV)
1247 uc->tchan = __udma_reserve_tchan(ud, uc->config.channel_tpl, -1);
1262 uc->rchan = __udma_reserve_rchan(ud, uc->config.channel_tpl, -1);
1452 if (uc->config.dir == DMA_MEM_TO_MEM)
1472 if (uc->config.pkt_mode)
1577 if (uc->config.pkt_mode) {
1579 fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib,
1580 uc->config.psd_size, 0);
1590 req_tx.tx_supr_tdpkt = uc->config.notdpkt;
1593 req_tx.tx_atype = uc->config.atype;
1615 if (uc->config.pkt_mode) {
1617 fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib,
1618 uc->config.psd_size, 0);
1630 req_rx.rx_atype = uc->config.atype;
1656 if (uc->config.needs_epib)
1660 if (uc->config.psd_size)
1678 dev_err(ud->dev, "flow%d config failed: %d\n", rchan->id, ret);
1692 if (uc->config.pkt_mode || uc->config.dir == DMA_MEM_TO_MEM) {
1695 if (uc->config.dir == DMA_MEM_TO_MEM) {
1696 uc->config.hdesc_size = cppi5_trdesc_calc_size(
1698 uc->config.pkt_mode = false;
1704 uc->config.hdesc_size,
1724 switch (uc->config.dir) {
1746 uc->config.src_thread = ud->psil_base + uc->tchan->id;
1747 uc->config.dst_thread = (ud->psil_base + uc->rchan->id) |
1764 uc->config.src_thread = ud->psil_base + uc->tchan->id;
1765 uc->config.dst_thread = uc->config.remote_thread_id;
1766 uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET;
1782 uc->config.src_thread = uc->config.remote_thread_id;
1783 uc->config.dst_thread = (ud->psil_base + uc->rchan->id) |
1794 __func__, uc->id, uc->config.dir);
1815 ret = navss_psil_pair(ud, uc->config.src_thread, uc->config.dst_thread);
1818 uc->config.src_thread, uc->config.dst_thread);
1840 if (is_slave_direction(uc->config.dir) && !uc->config.pkt_mode) {
1871 navss_psil_unpair(ud, uc->config.src_thread, uc->config.dst_thread);
1930 hwdesc->cppi5_desc_size = uc->config.hdesc_size;
2099 if (uc->config.ep_type != PSIL_EP_PDMA_XY)
2131 if (uc->config.pkt_mode || !uc->cyclic) {
2139 if (uc->config.dir == DMA_DEV_TO_MEM &&
2191 hwdesc->cppi5_desc_size = uc->config.hdesc_size;
2241 if (!uc->config.pkt_mode || !uc->config.metadata_size)
2244 if (!data || len > uc->config.metadata_size)
2247 if (uc->config.needs_epib && len < CPPI5_INFO0_HDESC_EPIB_SIZE)
2254 if (uc->config.needs_epib)
2259 if (uc->config.needs_epib)
2275 if (!uc->config.pkt_mode || !uc->config.metadata_size)
2280 *max_len = uc->config.metadata_size;
2298 if (!uc->config.pkt_mode || !uc->config.metadata_size)
2301 if (payload_len > uc->config.metadata_size)
2304 if (uc->config.needs_epib && payload_len < CPPI5_INFO0_HDESC_EPIB_SIZE)
2309 if (uc->config.needs_epib) {
2336 if (dir != uc->config.dir) {
2340 dmaengine_get_direction_text(uc->config.dir),
2359 if (uc->config.pkt_mode)
2384 if (uc->config.metadata_size)
2500 hwdesc->cppi5_desc_size = uc->config.hdesc_size;
2530 if (dir != uc->config.dir) {
2534 dmaengine_get_direction_text(uc->config.dir),
2555 if (uc->config.pkt_mode)
2581 if (uc->config.metadata_size)
2598 if (uc->config.dir != DMA_MEM_TO_MEM) {
2602 dmaengine_get_direction_text(uc->config.dir),
2665 if (uc->config.metadata_size)
2723 if (uc->config.ep_type != PSIL_EP_NATIVE) {
2733 if (uc->config.ep_type != PSIL_EP_NATIVE) {
2750 if (!residue && (uc->config.dir == DMA_DEV_TO_MEM || !delay)) {
2772 switch (uc->config.dir) {
2800 switch (uc->config.dir) {
2979 navss_psil_unpair(ud, uc->config.src_thread,
2980 uc->config.dst_thread);
3016 ucc = &uc->config;
3448 struct udma_chan_config *ucc = &uc->config;
3452 seq_printf(s, " (%s, ", dmaengine_get_direction_text(uc->config.dir));
3454 switch (uc->config.dir) {
3665 uc->config.remote_thread_id = -1;
3666 uc->config.dir = DMA_MEM_TO_MEM;