Lines Matching refs:req
205 struct ti_sci_msg_rm_udmap_tx_ch_cfg req;
207 memset(&req, 0, sizeof(req));
209 req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID |
217 req.nav_id = tisci_rm->tisci_dev_id;
218 req.index = tx_chn->udma_tchan_id;
220 req.tx_pause_on_err = 1;
222 req.tx_filt_einfo = 1;
224 req.tx_filt_pswords = 1;
225 req.tx_chan_type = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
227 req.tx_supr_tdpkt = 1;
228 req.tx_fetch_size = tx_chn->common.hdesc_size >> 2;
229 req.txcq_qnum = k3_ringacc_get_ring_id(tx_chn->ringtxcq);
230 req.tx_atype = tx_chn->common.atype;
232 return tisci_rm->tisci_udmap_ops->tx_ch_cfg(tisci_rm->tisci, &req);
493 struct ti_sci_msg_rm_udmap_rx_ch_cfg req;
496 memset(&req, 0, sizeof(req));
498 req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
505 req.nav_id = tisci_rm->tisci_dev_id;
506 req.index = rx_chn->udma_rchan_id;
507 req.rx_fetch_size = rx_chn->common.hdesc_size >> 2;
511 * req.rxcq_qnum = k3_ringacc_get_ring_id(rx_chn->flows[0].ringrx);
513 req.rxcq_qnum = 0xFFFF;
516 req.flowid_start = rx_chn->flow_id_base;
517 req.flowid_cnt = rx_chn->flow_num;
519 req.rx_chan_type = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
520 req.rx_atype = rx_chn->common.atype;
522 ret = tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req);
556 struct ti_sci_msg_rm_udmap_flow_cfg req;
605 memset(&req, 0, sizeof(req));
607 req.valid_params =
621 req.nav_id = tisci_rm->tisci_dev_id;
622 req.flow_index = flow->udma_rflow_id;
624 req.rx_einfo_present = 1;
626 req.rx_psinfo_present = 1;
628 req.rx_error_handling = 1;
629 req.rx_desc_type = 0;
630 req.rx_dest_qnum = rx_ring_id;
631 req.rx_src_tag_hi_sel = 0;
632 req.rx_src_tag_lo_sel = flow_cfg->src_tag_lo_sel;
633 req.rx_dest_tag_hi_sel = 0;
634 req.rx_dest_tag_lo_sel = 0;
635 req.rx_fdq0_sz0_qnum = rx_ringfdq_id;
636 req.rx_fdq1_qnum = rx_ringfdq_id;
637 req.rx_fdq2_qnum = rx_ringfdq_id;
638 req.rx_fdq3_qnum = rx_ringfdq_id;
640 ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci, &req);
979 struct ti_sci_msg_rm_udmap_flow_cfg req;
990 memset(&req, 0, sizeof(req));
992 req.valid_params =
998 req.nav_id = tisci_rm->tisci_dev_id;
999 req.flow_index = flow->udma_rflow_id;
1000 req.rx_dest_qnum = rx_ring_id;
1001 req.rx_fdq0_sz0_qnum = rx_ringfdq_id;
1002 req.rx_fdq1_qnum = rx_ringfdq_id;
1003 req.rx_fdq2_qnum = rx_ringfdq_id;
1004 req.rx_fdq3_qnum = rx_ringfdq_id;
1006 ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci, &req);
1022 struct ti_sci_msg_rm_udmap_flow_cfg req;
1028 memset(&req, 0, sizeof(req));
1029 req.valid_params =
1035 req.nav_id = tisci_rm->tisci_dev_id;
1036 req.flow_index = flow->udma_rflow_id;
1037 req.rx_dest_qnum = TI_SCI_RESOURCE_NULL;
1038 req.rx_fdq0_sz0_qnum = TI_SCI_RESOURCE_NULL;
1039 req.rx_fdq1_qnum = TI_SCI_RESOURCE_NULL;
1040 req.rx_fdq2_qnum = TI_SCI_RESOURCE_NULL;
1041 req.rx_fdq3_qnum = TI_SCI_RESOURCE_NULL;
1043 ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci, &req);