Lines Matching refs:echan
186 struct edma_chan *echan;
442 static void edma_set_chmap(struct edma_chan *echan, int slot)
444 struct edma_cc *ecc = echan->ecc;
445 int channel = EDMA_CHAN_SLOT(echan->ch_num);
453 static void edma_setup_interrupt(struct edma_chan *echan, bool enable)
455 struct edma_cc *ecc = echan->ecc;
456 int channel = EDMA_CHAN_SLOT(echan->ch_num);
598 static void edma_start(struct edma_chan *echan)
600 struct edma_cc *ecc = echan->ecc;
601 int channel = EDMA_CHAN_SLOT(echan->ch_num);
605 if (!echan->hw_triggered) {
625 static void edma_stop(struct edma_chan *echan)
627 struct edma_cc *ecc = echan->ecc;
628 int channel = EDMA_CHAN_SLOT(echan->ch_num);
652 static void edma_pause(struct edma_chan *echan)
654 int channel = EDMA_CHAN_SLOT(echan->ch_num);
656 edma_shadow0_write_array(echan->ecc, SH_EECR,
662 static void edma_resume(struct edma_chan *echan)
664 int channel = EDMA_CHAN_SLOT(echan->ch_num);
666 edma_shadow0_write_array(echan->ecc, SH_EESR,
671 static void edma_trigger_channel(struct edma_chan *echan)
673 struct edma_cc *ecc = echan->ecc;
674 int channel = EDMA_CHAN_SLOT(echan->ch_num);
684 static void edma_clean_channel(struct edma_chan *echan)
686 struct edma_cc *ecc = echan->ecc;
687 int channel = EDMA_CHAN_SLOT(echan->ch_num);
702 static void edma_assign_channel_eventq(struct edma_chan *echan,
705 struct edma_cc *ecc = echan->ecc;
706 int channel = EDMA_CHAN_SLOT(echan->ch_num);
720 static int edma_alloc_channel(struct edma_chan *echan,
723 struct edma_cc *ecc = echan->ecc;
724 int channel = EDMA_CHAN_SLOT(echan->ch_num);
726 if (!test_bit(echan->ch_num, ecc->channels_mask)) {
728 echan->ch_num);
737 edma_stop(echan);
739 edma_setup_interrupt(echan, true);
741 edma_assign_channel_eventq(echan, eventq_no);
746 static void edma_free_channel(struct edma_chan *echan)
749 edma_stop(echan);
751 edma_setup_interrupt(echan, false);
775 static void edma_execute(struct edma_chan *echan)
777 struct edma_cc *ecc = echan->ecc;
780 struct device *dev = echan->vchan.chan.device->dev;
783 if (!echan->edesc) {
785 vdesc = vchan_next_desc(&echan->vchan);
789 echan->edesc = to_edma_desc(&vdesc->tx);
792 edesc = echan->edesc;
802 edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param);
816 j, echan->ch_num, echan->slot[i],
827 edma_link(ecc, echan->slot[i], echan->slot[i + 1]);
839 edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]);
841 edma_link(ecc, echan->slot[nslots - 1],
842 echan->ecc->dummy_slot);
845 if (echan->missed) {
851 dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
852 edma_clean_channel(echan);
853 edma_stop(echan);
854 edma_start(echan);
855 edma_trigger_channel(echan);
856 echan->missed = 0;
859 echan->ch_num);
860 edma_start(echan);
863 echan->ch_num, edesc->processed);
864 edma_resume(echan);
870 struct edma_chan *echan = to_edma_chan(chan);
874 spin_lock_irqsave(&echan->vchan.lock, flags);
879 * echan->edesc is NULL and exit.)
881 if (echan->edesc) {
882 edma_stop(echan);
884 if (!echan->tc && echan->edesc->cyclic)
885 edma_assign_channel_eventq(echan, EVENTQ_DEFAULT);
887 vchan_terminate_vdesc(&echan->edesc->vdesc);
888 echan->edesc = NULL;
891 vchan_get_all_descriptors(&echan->vchan, &head);
892 spin_unlock_irqrestore(&echan->vchan.lock, flags);
893 vchan_dma_desc_free_list(&echan->vchan, &head);
900 struct edma_chan *echan = to_edma_chan(chan);
902 vchan_synchronize(&echan->vchan);
908 struct edma_chan *echan = to_edma_chan(chan);
918 memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
925 struct edma_chan *echan = to_edma_chan(chan);
927 if (!echan->edesc)
930 edma_pause(echan);
936 struct edma_chan *echan = to_edma_chan(chan);
938 edma_resume(echan);
958 struct edma_chan *echan = to_edma_chan(chan);
1043 param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
1071 struct edma_chan *echan = to_edma_chan(chan);
1080 if (unlikely(!echan || !sgl || !sg_len))
1084 src_addr = echan->cfg.src_addr;
1085 dev_width = echan->cfg.src_addr_width;
1086 burst = echan->cfg.src_maxburst;
1088 dst_addr = echan->cfg.dst_addr;
1089 dev_width = echan->cfg.dst_addr_width;
1090 burst = echan->cfg.dst_maxburst;
1108 edesc->echan = echan;
1114 if (echan->slot[i] < 0) {
1115 echan->slot[i] =
1116 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1117 if (echan->slot[i] < 0) {
1159 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1169 struct edma_chan *echan = to_edma_chan(chan);
1172 if (unlikely(!echan || !len))
1225 edesc->echan = echan;
1245 if (echan->slot[1] < 0) {
1246 echan->slot[1] = edma_alloc_slot(echan->ecc,
1248 if (echan->slot[1] < 0) {
1275 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1284 struct edma_chan *echan = to_edma_chan(chan);
1330 edesc->echan = echan;
1342 param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
1350 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1358 struct edma_chan *echan = to_edma_chan(chan);
1367 if (unlikely(!echan || !buf_len || !period_len))
1371 src_addr = echan->cfg.src_addr;
1373 dev_width = echan->cfg.src_addr_width;
1374 burst = echan->cfg.src_maxburst;
1377 dst_addr = echan->cfg.dst_addr;
1378 dev_width = echan->cfg.dst_addr_width;
1379 burst = echan->cfg.dst_maxburst;
1429 edesc->echan = echan;
1432 __func__, echan->ch_num, nslots, period_len, buf_len);
1436 if (echan->slot[i] < 0) {
1437 echan->slot[i] =
1438 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1439 if (echan->slot[i] < 0) {
1479 i, echan->ch_num, echan->slot[i],
1504 if (!echan->tc)
1505 edma_assign_channel_eventq(echan, EVENTQ_0);
1507 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1510 static void edma_completion_handler(struct edma_chan *echan)
1512 struct device *dev = echan->vchan.chan.device->dev;
1515 spin_lock(&echan->vchan.lock);
1516 edesc = echan->edesc;
1520 spin_unlock(&echan->vchan.lock);
1524 edma_stop(echan);
1526 echan->edesc = NULL;
1529 echan->ch_num);
1532 echan->ch_num);
1534 edma_pause(echan);
1541 edma_execute(echan);
1544 spin_unlock(&echan->vchan.lock);
1593 static void edma_error_handler(struct edma_chan *echan)
1595 struct edma_cc *ecc = echan->ecc;
1596 struct device *dev = echan->vchan.chan.device->dev;
1600 if (!echan->edesc)
1603 spin_lock(&echan->vchan.lock);
1605 err = edma_read_slot(ecc, echan->slot[0], &p);
1621 echan->missed = 1;
1628 edma_clean_channel(echan);
1629 edma_stop(echan);
1630 edma_start(echan);
1631 edma_trigger_channel(echan);
1633 spin_unlock(&echan->vchan.lock);
1725 struct edma_chan *echan = to_edma_chan(chan);
1726 struct edma_cc *ecc = echan->ecc;
1731 if (echan->tc) {
1732 eventq_no = echan->tc->id;
1735 echan->tc = &ecc->tc_list[ecc->info->default_queue];
1736 eventq_no = echan->tc->id;
1739 ret = edma_alloc_channel(echan, eventq_no);
1743 echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num);
1744 if (echan->slot[0] < 0) {
1746 EDMA_CHAN_SLOT(echan->ch_num));
1747 ret = echan->slot[0];
1752 edma_set_chmap(echan, echan->slot[0]);
1753 echan->alloced = true;
1756 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id,
1757 echan->hw_triggered ? "HW" : "SW");
1762 edma_free_channel(echan);
1769 struct edma_chan *echan = to_edma_chan(chan);
1770 struct device *dev = echan->ecc->dev;
1774 edma_stop(echan);
1776 vchan_free_chan_resources(&echan->vchan);
1780 if (echan->slot[i] >= 0) {
1781 edma_free_slot(echan->ecc, echan->slot[i]);
1782 echan->slot[i] = -1;
1787 edma_set_chmap(echan, echan->ecc->dummy_slot);
1790 if (echan->alloced) {
1791 edma_free_channel(echan);
1792 echan->alloced = false;
1795 echan->tc = NULL;
1796 echan->hw_triggered = false;
1799 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id);
1805 struct edma_chan *echan = to_edma_chan(chan);
1808 spin_lock_irqsave(&echan->vchan.lock, flags);
1809 if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
1810 edma_execute(echan);
1811 spin_unlock_irqrestore(&echan->vchan.lock, flags);
1827 struct edma_chan *echan = edesc->echan;
1830 int channel = EDMA_CHAN_SLOT(echan->ch_num);
1840 pos = edma_get_position(echan->ecc, echan->slot[0], dst);
1856 while (edma_shadow0_read_array(echan->ecc, event_reg, idx) & ch_bit) {
1857 pos = edma_get_position(echan->ecc, echan->slot[0], dst);
1862 dev_dbg_ratelimited(echan->vchan.chan.device->dev,
1917 struct edma_chan *echan = to_edma_chan(chan);
1931 spin_lock_irqsave(&echan->vchan.lock, flags);
1932 if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) {
1933 txstate->residue = edma_residue(echan->edesc);
1935 struct virt_dma_desc *vdesc = vchan_find_desc(&echan->vchan,
1949 echan->edesc && echan->edesc->polled &&
1950 echan->edesc->vdesc.tx.cookie == cookie) {
1951 edma_stop(echan);
1952 vchan_cookie_complete(&echan->edesc->vdesc);
1953 echan->edesc = NULL;
1954 edma_execute(echan);
1958 spin_unlock_irqrestore(&echan->vchan.lock, flags);
2060 struct edma_chan *echan = &ecc->slave_chans[i];
2061 echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i);
2062 echan->ecc = ecc;
2063 echan->vchan.desc_free = edma_desc_free;
2066 vchan_init(&echan->vchan, m_ddev);
2068 vchan_init(&echan->vchan, s_ddev);
2070 INIT_LIST_HEAD(&echan->node);
2072 echan->slot[j] = -1;
2292 struct edma_chan *echan;
2299 echan = &ecc->slave_chans[i];
2300 if (echan->ch_num == dma_spec->args[0]) {
2301 chan = &echan->vchan.chan;
2309 if (echan->ecc->legacy_mode && dma_spec->args_count == 1)
2312 if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 &&
2313 dma_spec->args[1] < echan->ecc->num_tc) {
2314 echan->tc = &echan->ecc->tc_list[dma_spec->args[1]];
2321 echan->hw_triggered = true;
2612 struct edma_chan *echan, *_echan;
2614 list_for_each_entry_safe(echan, _echan,
2616 list_del(&echan->vchan.chan.device_node);
2617 tasklet_kill(&echan->vchan.task);
2647 struct edma_chan *echan = ecc->slave_chans;
2651 if (echan[i].alloced)
2652 edma_setup_interrupt(&echan[i], false);
2661 struct edma_chan *echan = ecc->slave_chans;
2676 if (echan[i].alloced) {
2682 edma_setup_interrupt(&echan[i], true);
2685 edma_set_chmap(&echan[i], echan[i].slot[0]);
2726 struct edma_chan *echan = to_edma_chan(chan);
2728 if (ch_req == echan->ch_num) {
2730 echan->hw_triggered = true;