Lines Matching defs:channel
51 /* Offsets for EDMA CC global channel registers and their shadows */
98 #define EDMA_M 0x1000 /* global channel registers */
120 * Max of 20 segments per channel to conserve PaRAM slots
138 * reg0: channel/event 0-31
139 * reg1: channel/event 32-63
141 * bit 5 in the channel number tells the array index (0/1)
144 #define EDMA_REG_ARRAY_INDEX(channel) ((channel) >> 5)
145 #define EDMA_CHANNEL_BIT(channel) (BIT((channel) & 0x1f))
265 * If the bit is cleared, the channel is allocated to be used by DSP
445 int channel = EDMA_CHAN_SLOT(echan->ch_num);
449 edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5));
456 int channel = EDMA_CHAN_SLOT(echan->ch_num);
457 int idx = EDMA_REG_ARRAY_INDEX(channel);
458 int ch_bit = EDMA_CHANNEL_BIT(channel);
498 * mapped to a hardware DMA channel, and will normally be used by
499 * linking to them from a slot associated with a DMA channel.
510 /* Requesting entry paRAM slot for a HW triggered channel. */
601 int channel = EDMA_CHAN_SLOT(echan->ch_num);
602 int idx = EDMA_REG_ARRAY_INDEX(channel);
603 int ch_bit = EDMA_CHANNEL_BIT(channel);
611 /* EDMA channel with event association */
628 int channel = EDMA_CHAN_SLOT(echan->ch_num);
629 int idx = EDMA_REG_ARRAY_INDEX(channel);
630 int ch_bit = EDMA_CHANNEL_BIT(channel);
649 * Temporarily disable EDMA hardware events on the specified channel,
654 int channel = EDMA_CHAN_SLOT(echan->ch_num);
657 EDMA_REG_ARRAY_INDEX(channel),
658 EDMA_CHANNEL_BIT(channel));
661 /* Re-enable EDMA hardware events on the specified channel. */
664 int channel = EDMA_CHAN_SLOT(echan->ch_num);
667 EDMA_REG_ARRAY_INDEX(channel),
668 EDMA_CHANNEL_BIT(channel));
674 int channel = EDMA_CHAN_SLOT(echan->ch_num);
675 int idx = EDMA_REG_ARRAY_INDEX(channel);
676 int ch_bit = EDMA_CHANNEL_BIT(channel);
687 int channel = EDMA_CHAN_SLOT(echan->ch_num);
688 int idx = EDMA_REG_ARRAY_INDEX(channel);
689 int ch_bit = EDMA_CHANNEL_BIT(channel);
701 /* Move channel to a specific event queue */
706 int channel = EDMA_CHAN_SLOT(echan->ch_num);
707 int bit = (channel & 0x7) * 4;
716 edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit),
724 int channel = EDMA_CHAN_SLOT(echan->ch_num);
733 edma_or_array2(ecc, EDMA_DRAE, 0, EDMA_REG_ARRAY_INDEX(channel),
734 EDMA_CHANNEL_BIT(channel));
851 dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
858 dev_dbg(dev, "first transfer starting on channel %d\n",
883 /* Move the cyclic channel back to default queue */
1431 dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
1503 /* Place the cyclic channel to highest priority queue */
1528 dev_dbg(dev, "Transfer completed on channel %d\n",
1531 dev_dbg(dev, "Sub transfer completed on channel %d\n",
1576 u32 channel;
1582 channel = (bank << 5) | slot;
1585 edma_completion_handler(&ecc->slave_chans[channel]);
1722 /* Alloc channel resources */
1734 /* memcpy channel */
1745 dev_err(dev, "Entry slot allocation failed for channel %u\n",
1751 /* Set up channel -> slot mapping for the entry slot */
1755 dev_dbg(dev, "Got eDMA channel %d for virt channel %d (%s trigger)\n",
1766 /* Free channel resources */
1789 /* Free EDMA channel */
1798 dev_dbg(dev, "Free eDMA channel %d for virt channel %d\n",
1830 int channel = EDMA_CHAN_SLOT(echan->ch_num);
1831 int idx = EDMA_REG_ARRAY_INDEX(channel);
1832 int ch_bit = EDMA_CHANNEL_BIT(channel);
1846 * 1. while and event is pending for the channel
2320 /* The channel is going to be used as HW synchronized */
2536 /* See if we have optional dma-channel-mask array */
2539 "dma-channel-mask",
2543 dev_warn(dev, "dma-channel-mask is not complete.\n");
2546 "dma-channel-mask is out of range or empty\n");
2684 /* Set up channel -> slot mapping for the entry slot */
2729 /* The channel is going to be used as HW synchronized */