Lines Matching defs:tdc
180 static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val)
182 writel(val, tdc->chan_addr + reg);
185 static inline u32 tdma_ch_read(struct tegra_adma_chan *tdc, u32 reg)
187 return readl(tdc->chan_addr + reg);
201 static inline struct device *tdc2dev(struct tegra_adma_chan *tdc)
203 return tdc->tdma->dev;
214 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
216 memcpy(&tdc->sconfig, sconfig, sizeof(*sconfig));
247 static int tegra_adma_request_alloc(struct tegra_adma_chan *tdc,
250 struct tegra_adma *tdma = tdc->tdma;
251 unsigned int sreq_index = tdc->sreq_index;
253 if (tdc->sreq_reserved)
254 return tdc->sreq_dir == direction ? 0 : -EINVAL;
278 dma_chan_name(&tdc->vc.chan));
282 tdc->sreq_dir = direction;
283 tdc->sreq_reserved = true;
288 static void tegra_adma_request_free(struct tegra_adma_chan *tdc)
290 struct tegra_adma *tdma = tdc->tdma;
292 if (!tdc->sreq_reserved)
295 switch (tdc->sreq_dir) {
297 clear_bit(tdc->sreq_index, &tdma->tx_requests_reserved);
301 clear_bit(tdc->sreq_index, &tdma->rx_requests_reserved);
306 dma_chan_name(&tdc->vc.chan));
310 tdc->sreq_reserved = false;
313 static u32 tegra_adma_irq_status(struct tegra_adma_chan *tdc)
315 u32 status = tdma_ch_read(tdc, ADMA_CH_INT_STATUS);
320 static u32 tegra_adma_irq_clear(struct tegra_adma_chan *tdc)
322 u32 status = tegra_adma_irq_status(tdc);
325 tdma_ch_write(tdc, ADMA_CH_INT_CLEAR, status);
330 static void tegra_adma_stop(struct tegra_adma_chan *tdc)
335 tdma_ch_write(tdc, ADMA_CH_CMD, 0);
338 tegra_adma_irq_clear(tdc);
340 if (readx_poll_timeout_atomic(readl, tdc->chan_addr + ADMA_CH_STATUS,
343 dev_err(tdc2dev(tdc), "unable to stop DMA channel\n");
347 kfree(tdc->desc);
348 tdc->desc = NULL;
351 static void tegra_adma_start(struct tegra_adma_chan *tdc)
353 struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc);
365 dev_warn(tdc2dev(tdc), "unable to start DMA, no descriptor\n");
371 tdc->tx_buf_pos = 0;
372 tdc->tx_buf_count = 0;
373 tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc);
374 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
375 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr);
376 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr);
377 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl);
378 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config);
381 tdma_ch_write(tdc, ADMA_CH_CMD, 1);
383 tdc->desc = desc;
386 static unsigned int tegra_adma_get_residue(struct tegra_adma_chan *tdc)
388 struct tegra_adma_desc *desc = tdc->desc;
390 unsigned int pos = tdma_ch_read(tdc, ADMA_CH_XFER_STATUS);
396 if (pos < tdc->tx_buf_pos)
397 tdc->tx_buf_count += pos + (max - tdc->tx_buf_pos);
399 tdc->tx_buf_count += pos - tdc->tx_buf_pos;
401 periods_remaining = tdc->tx_buf_count % desc->num_periods;
402 tdc->tx_buf_pos = pos;
409 struct tegra_adma_chan *tdc = dev_id;
413 spin_lock_irqsave(&tdc->vc.lock, flags);
415 status = tegra_adma_irq_clear(tdc);
416 if (status == 0 || !tdc->desc) {
417 spin_unlock_irqrestore(&tdc->vc.lock, flags);
421 vchan_cyclic_callback(&tdc->desc->vd);
423 spin_unlock_irqrestore(&tdc->vc.lock, flags);
430 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
433 spin_lock_irqsave(&tdc->vc.lock, flags);
435 if (vchan_issue_pending(&tdc->vc)) {
436 if (!tdc->desc)
437 tegra_adma_start(tdc);
440 spin_unlock_irqrestore(&tdc->vc.lock, flags);
443 static bool tegra_adma_is_paused(struct tegra_adma_chan *tdc)
447 csts = tdma_ch_read(tdc, ADMA_CH_STATUS);
455 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
456 struct tegra_adma_desc *desc = tdc->desc;
460 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
462 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
464 while (dcnt-- && !tegra_adma_is_paused(tdc))
468 dev_err(tdc2dev(tdc), "unable to pause DMA channel\n");
477 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
478 struct tegra_adma_desc *desc = tdc->desc;
481 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
483 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
490 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
494 spin_lock_irqsave(&tdc->vc.lock, flags);
496 if (tdc->desc)
497 tegra_adma_stop(tdc);
499 tegra_adma_request_free(tdc);
500 vchan_get_all_descriptors(&tdc->vc, &head);
501 spin_unlock_irqrestore(&tdc->vc.lock, flags);
502 vchan_dma_desc_free_list(&tdc->vc, &head);
511 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
522 spin_lock_irqsave(&tdc->vc.lock, flags);
524 vd = vchan_find_desc(&tdc->vc, cookie);
528 } else if (tdc->desc && tdc->desc->vd.tx.cookie == cookie) {
529 residual = tegra_adma_get_residue(tdc);
534 spin_unlock_irqrestore(&tdc->vc.lock, flags);
557 static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc,
563 const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata;
572 burst_size = tdc->sconfig.dst_maxburst;
574 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
582 burst_size = tdc->sconfig.src_maxburst;
584 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
591 dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
605 return tegra_adma_request_alloc(tdc, direction);
613 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
617 dev_err(tdc2dev(tdc), "invalid buffer/period len\n");
622 dev_err(tdc2dev(tdc), "buf_len not a multiple of period_len\n");
627 dev_err(tdc2dev(tdc), "invalid buffer alignment\n");
639 if (tegra_adma_set_xfer_params(tdc, desc, buf_addr, direction)) {
644 return vchan_tx_prep(&tdc->vc, &desc->vd, flags);
649 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
652 ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc);
654 dev_err(tdc2dev(tdc), "failed to get interrupt for %s\n",
659 ret = pm_runtime_get_sync(tdc2dev(tdc));
661 pm_runtime_put_noidle(tdc2dev(tdc));
662 free_irq(tdc->irq, tdc);
666 dma_cookie_init(&tdc->vc.chan);
673 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
676 vchan_free_chan_resources(&tdc->vc);
677 tasklet_kill(&tdc->vc.task);
678 free_irq(tdc->irq, tdc);
679 pm_runtime_put(tdc2dev(tdc));
681 tdc->sreq_index = 0;
682 tdc->sreq_dir = DMA_TRANS_NONE;
689 struct tegra_adma_chan *tdc;
707 tdc = to_tegra_adma_chan(chan);
708 tdc->sreq_index = sreq_index;
717 struct tegra_adma_chan *tdc;
725 tdc = &tdma->channels[i];
726 ch_reg = &tdc->ch_regs;
727 ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD);
731 ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC);
732 ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR);
733 ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR);
734 ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
735 ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL);
736 ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG);
749 struct tegra_adma_chan *tdc;
763 tdc = &tdma->channels[i];
764 ch_reg = &tdc->ch_regs;
768 tdma_ch_write(tdc, ADMA_CH_TC, ch_reg->tc);
769 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_reg->src_addr);
770 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_reg->trg_addr);
771 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl);
772 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl);
773 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config);
774 tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd);
854 struct tegra_adma_chan *tdc = &tdma->channels[i];
856 tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset
859 tdc->irq = of_irq_get(pdev->dev.of_node, i);
860 if (tdc->irq <= 0) {
861 ret = tdc->irq ?: -ENXIO;
865 vchan_init(&tdc->vc, &tdma->dma_dev);
866 tdc->vc.desc_free = tegra_adma_desc_free;
867 tdc->tdma = tdma;