Lines Matching refs:status
104 * on-flight burst and update DMA status register.
161 * This descriptor keep track of transfer status, callbacks and request
419 u32 csr, status;
430 /* Clear interrupt status if it is there */
431 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
432 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
434 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
460 unsigned long status;
465 * If there is no IEC status then this makes sure that last burst
470 * If there is already IEC status then interrupt handler need to
474 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
480 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
527 unsigned long status)
529 return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
676 u32 status;
681 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
682 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
683 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
692 dev_info(tdc2dev(tdc), "Interrupt already served status 0x%08x\n",
693 status);
754 u32 status, wcount;
762 /* Pause DMA before checking the queue status */
765 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
766 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
769 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
774 wcount = status;
807 u32 status;
810 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
813 return !(status & TEGRA_APBDMA_STATUS_ISE_EOC);
842 u32 status, wcount = 0;
850 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
853 wcount = status;
855 if (status & TEGRA_APBDMA_STATUS_ISE_EOC)
867 * The alternative would be to poll the status register
916 /* Check on wait_ack desc status */