Lines Matching defs:hwdesc
245 struct stm32_mdma_hwdesc *hwdesc;
346 desc->node[i].hwdesc =
349 if (!desc->node[i].hwdesc)
360 dma_pool_free(chan->desc_pool, desc->node[i].hwdesc,
373 dma_pool_free(chan->desc_pool, desc->node[i].hwdesc,
675 dev_dbg(chan2dev(chan), "hwdesc: %pad\n", &node->hwdesc_phys);
676 dev_dbg(chan2dev(chan), "CTCR: 0x%08x\n", node->hwdesc->ctcr);
677 dev_dbg(chan2dev(chan), "CBNDTR: 0x%08x\n", node->hwdesc->cbndtr);
678 dev_dbg(chan2dev(chan), "CSAR: 0x%08x\n", node->hwdesc->csar);
679 dev_dbg(chan2dev(chan), "CDAR: 0x%08x\n", node->hwdesc->cdar);
680 dev_dbg(chan2dev(chan), "CBRUR: 0x%08x\n", node->hwdesc->cbrur);
681 dev_dbg(chan2dev(chan), "CLAR: 0x%08x\n", node->hwdesc->clar);
682 dev_dbg(chan2dev(chan), "CTBR: 0x%08x\n", node->hwdesc->ctbr);
683 dev_dbg(chan2dev(chan), "CMAR: 0x%08x\n", node->hwdesc->cmar);
684 dev_dbg(chan2dev(chan), "CMDR: 0x%08x\n\n", node->hwdesc->cmdr);
695 struct stm32_mdma_hwdesc *hwdesc;
698 hwdesc = desc->node[count].hwdesc;
699 hwdesc->ctcr = ctcr;
700 hwdesc->cbndtr &= ~(STM32_MDMA_CBNDTR_BRC_MK |
704 hwdesc->cbndtr |= STM32_MDMA_CBNDTR_BNDT(len);
705 hwdesc->csar = src_addr;
706 hwdesc->cdar = dst_addr;
707 hwdesc->cbrur = 0;
708 hwdesc->ctbr = ctbr;
709 hwdesc->cmar = config->mask_addr;
710 hwdesc->cmdr = config->mask_data;
714 hwdesc->clar = desc->node[0].hwdesc_phys;
716 hwdesc->clar = 0;
718 hwdesc->clar = desc->node[next].hwdesc_phys;
812 dma_pool_free(chan->desc_pool, desc->node[i].hwdesc,
882 /* Configure hwdesc list */
903 dma_pool_free(chan->desc_pool, desc->node[i].hwdesc,
917 struct stm32_mdma_hwdesc *hwdesc;
1018 hwdesc = desc->node[0].hwdesc;
1019 hwdesc->ctcr = ctcr;
1020 hwdesc->cbndtr = cbndtr;
1021 hwdesc->csar = src;
1022 hwdesc->cdar = dest;
1023 hwdesc->cbrur = 0;
1024 hwdesc->clar = 0;
1025 hwdesc->ctbr = ctbr;
1026 hwdesc->cmar = 0;
1027 hwdesc->cmdr = 0;
1118 struct stm32_mdma_hwdesc *hwdesc;
1131 hwdesc = chan->desc->node[0].hwdesc;
1135 stm32_mdma_write(dmadev, STM32_MDMA_CTCR(id), hwdesc->ctcr);
1136 stm32_mdma_write(dmadev, STM32_MDMA_CBNDTR(id), hwdesc->cbndtr);
1137 stm32_mdma_write(dmadev, STM32_MDMA_CSAR(id), hwdesc->csar);
1138 stm32_mdma_write(dmadev, STM32_MDMA_CDAR(id), hwdesc->cdar);
1139 stm32_mdma_write(dmadev, STM32_MDMA_CBRUR(id), hwdesc->cbrur);
1140 stm32_mdma_write(dmadev, STM32_MDMA_CLAR(id), hwdesc->clar);
1141 stm32_mdma_write(dmadev, STM32_MDMA_CTBR(id), hwdesc->ctbr);
1142 stm32_mdma_write(dmadev, STM32_MDMA_CMAR(id), hwdesc->cmar);
1143 stm32_mdma_write(dmadev, STM32_MDMA_CMDR(id), hwdesc->cmdr);
1156 if (hwdesc->ctcr & STM32_MDMA_CTCR_SWRM) {
1205 struct stm32_mdma_hwdesc *hwdesc;
1213 hwdesc = chan->desc->node[chan->curr_hwdesc].hwdesc;
1232 if (hwdesc->ctcr & STM32_MDMA_CTCR_SWRM)
1285 struct stm32_mdma_hwdesc *hwdesc = desc->node[0].hwdesc;
1291 hwdesc = desc->node[i].hwdesc;
1292 residue += STM32_MDMA_CBNDTR_BNDT(hwdesc->cbndtr);