Lines Matching refs:dmadev
240 static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg)
242 return readl_relaxed(dmadev->base + reg);
245 static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val)
247 writel_relaxed(val, dmadev->base + reg);
391 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
403 dma_isr = stm32_dma_read(dmadev, STM32_DMA_HISR);
405 dma_isr = stm32_dma_read(dmadev, STM32_DMA_LISR);
414 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
428 stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr);
430 stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr);
435 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
440 dma_scr = stm32_dma_read(dmadev, reg);
444 stm32_dma_write(dmadev, reg, dma_scr);
446 return readl_relaxed_poll_timeout_atomic(dmadev->base + reg,
456 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
461 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
463 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
464 dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
466 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr);
515 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
516 u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
517 u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
518 u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id));
519 u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id));
520 u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id));
521 u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
535 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
564 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
565 stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar);
566 stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar);
567 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr);
568 stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar);
569 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr);
585 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
594 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
599 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
609 stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);
611 stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)));
614 stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);
616 stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)));
642 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
648 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
649 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
1042 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1044 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
1046 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
1065 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1070 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
1078 dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(id));
1082 dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(id));
1185 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1190 ret = pm_runtime_resume_and_get(dmadev->ddev.dev);
1196 pm_runtime_put(dmadev->ddev.dev);
1204 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1216 pm_runtime_put(dmadev->ddev.dev);
1245 struct stm32_dma_device *dmadev = ofdma->of_dma_data;
1246 struct device *dev = dmadev->ddev.dev;
1267 chan = &dmadev->chan[cfg.channel_id];
1289 struct stm32_dma_device *dmadev;
1302 dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
1303 if (!dmadev)
1306 dd = &dmadev->ddev;
1309 dmadev->base = devm_ioremap_resource(&pdev->dev, res);
1310 if (IS_ERR(dmadev->base))
1311 return PTR_ERR(dmadev->base);
1313 dmadev->clk = devm_clk_get(&pdev->dev, NULL);
1314 if (IS_ERR(dmadev->clk))
1315 return dev_err_probe(&pdev->dev, PTR_ERR(dmadev->clk), "Can't get clock\n");
1317 ret = clk_prepare_enable(dmadev->clk);
1323 dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node,
1365 if (dmadev->mem2mem) {
1372 chan = &dmadev->chan[i];
1383 chan = &dmadev->chan[i];
1401 stm32_dma_of_xlate, dmadev);
1408 platform_set_drvdata(pdev, dmadev);
1422 clk_disable_unprepare(dmadev->clk);
1430 struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1432 clk_disable_unprepare(dmadev->clk);
1439 struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1442 ret = clk_prepare_enable(dmadev->clk);
1455 struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1463 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));