Lines Matching defs:chan_reg
186 struct stm32_dma_chan_reg chan_reg;
205 struct stm32_dma_chan_reg chan_reg;
365 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK;
366 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE;
370 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE;
373 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
561 reg = &sg_req->chan_reg;
608 dma_sm0ar = sg_req->chan_reg.dma_sm0ar;
613 dma_sm1ar = sg_req->chan_reg.dma_sm1ar;
761 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
763 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth);
766 chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr;
811 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
813 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth);
816 chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr;
828 chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK |
831 chan->chan_reg.dma_scr |= dma_scr;
869 chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL;
871 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
887 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
888 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
889 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
890 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
891 desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg);
892 desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg);
893 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
955 chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC;
957 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;
960 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
971 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
972 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
973 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
974 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
975 desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr;
976 desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr;
977 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
1015 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
1016 desc->sg_req[i].chan_reg.dma_scr =
1024 desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
1025 desc->sg_req[i].chan_reg.dma_sfcr |=
1027 desc->sg_req[i].chan_reg.dma_spar = src + offset;
1028 desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset;
1029 desc->sg_req[i].chan_reg.dma_sndtr = xfer_count;
1079 return (dma_smar == sg_req->chan_reg.dma_sm0ar);
1084 return (dma_smar == sg_req->chan_reg.dma_sm1ar);
1229 stm32_dma_clear_reg(&chan->chan_reg);
1231 chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK;
1232 chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line);
1235 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;