Lines Matching refs:virtbase
525 * @virtbase: The virtual base address of the DMA's register.
570 void __iomem *virtbase;
620 return chan->base->virtbase + D40_DREG_PCBASE +
1057 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1059 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1274 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1276 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1358 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1363 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1656 regs[i] = readl(base->virtbase + il[i].src);
1684 writel(BIT(idx), base->virtbase + il[row].clr);
2062 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
2064 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
2322 writel(bit, d40c->base->virtbase + prioreg + group * 4);
2323 writel(bit, d40c->base->virtbase + rtreg + group * 4);
2963 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
2973 dma40_backup(base->virtbase, base->reg_val_backup,
2979 dma40_backup(base->virtbase, base->reg_val_backup_v4,
2994 base->virtbase + D40_DREG_GCC);
3006 base->virtbase + D40_DREG_GCC);
3028 val[0] = readl(base->virtbase + D40_DREG_PRSME);
3029 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
3079 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
3098 writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3108 void __iomem *virtbase;
3141 virtbase = ioremap(res->start, resource_size(res));
3142 if (!virtbase)
3147 pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
3150 cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
3182 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
3210 base->virtbase = virtbase;
3306 iounmap(virtbase);
3331 base->virtbase + dma_init_reg[i].reg);
3356 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
3357 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
3358 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
3359 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
3362 writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
3365 writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
3448 base->virtbase + D40_DREG_LCLA);
3557 val = readl(base->virtbase + D40_DREG_LCPA);
3563 writel(res->start, base->virtbase + D40_DREG_LCPA);
3588 writel(res->start, base->virtbase + D40_DREG_LCLA);
3632 writel_relaxed(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3664 if (base->virtbase)
3665 iounmap(base->virtbase);