Lines Matching defs:gen_dmac
563 * @gen_dmac: the struct for generic registers values to represent u8500/8540
600 struct d40_gen_dmac gen_dmac;
1649 struct d40_interrupt_lookup *il = base->gen_dmac.il;
1650 u32 il_size = base->gen_dmac.il_size;
2302 struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;
2978 if (base->gen_dmac.backup)
2980 base->gen_dmac.backup,
2981 base->gen_dmac.backup_size,
3217 base->gen_dmac.backup = d40_backup_regs_v4b;
3218 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B;
3219 base->gen_dmac.interrupt_en = D40_DREG_CPCMIS;
3220 base->gen_dmac.interrupt_clear = D40_DREG_CPCICR;
3221 base->gen_dmac.realtime_en = D40_DREG_CRSEG1;
3222 base->gen_dmac.realtime_clear = D40_DREG_CRCEG1;
3223 base->gen_dmac.high_prio_en = D40_DREG_CPSEG1;
3224 base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1;
3225 base->gen_dmac.il = il_v4b;
3226 base->gen_dmac.il_size = ARRAY_SIZE(il_v4b);
3227 base->gen_dmac.init_reg = dma_init_reg_v4b;
3228 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b);
3231 base->gen_dmac.backup = d40_backup_regs_v4a;
3232 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A;
3234 base->gen_dmac.interrupt_en = D40_DREG_PCMIS;
3235 base->gen_dmac.interrupt_clear = D40_DREG_PCICR;
3236 base->gen_dmac.realtime_en = D40_DREG_RSEG1;
3237 base->gen_dmac.realtime_clear = D40_DREG_RCEG1;
3238 base->gen_dmac.high_prio_en = D40_DREG_PSEG1;
3239 base->gen_dmac.high_prio_clear = D40_DREG_PCEG1;
3240 base->gen_dmac.il = il_v4a;
3241 base->gen_dmac.il_size = ARRAY_SIZE(il_v4a);
3242 base->gen_dmac.init_reg = dma_init_reg_v4a;
3243 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a);
3277 base->regs_interrupt = kmalloc_array(base->gen_dmac.il_size,
3326 struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg;
3327 u32 reg_size = base->gen_dmac.init_reg_size;
3362 writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
3365 writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
3368 base->gen_dmac.init_reg = NULL;
3369 base->gen_dmac.init_reg_size = 0;