Lines Matching defs:val
242 u32 mask, u32 val)
247 tmp = (orig & ~mask) | val;
252 u32 mask, u32 val)
257 tmp = (orig & ~mask) | val;
437 u32 val, chn = schan->chn_num + 1;
441 val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
442 val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
443 val |= SPRD_DMA_GLB_2STAGE_EN;
445 val |= SPRD_DMA_GLB_SRC_INT;
447 sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
451 val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
452 val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
453 val |= SPRD_DMA_GLB_2STAGE_EN;
455 val |= SPRD_DMA_GLB_SRC_INT;
457 sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
461 val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
463 val |= SPRD_DMA_GLB_2STAGE_EN;
465 val |= SPRD_DMA_GLB_DEST_INT;
467 sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
471 val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
473 val |= SPRD_DMA_GLB_2STAGE_EN;
475 val |= SPRD_DMA_GLB_DEST_INT;
477 sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
492 u32 reg, val, req_id;
502 val = BIT(req_id);
505 val = BIT(req_id - 32);
508 sprd_dma_glb_update(sdev, reg, val, enable ? val : 0);