Lines Matching defs:base
122 void __iomem *base;
127 int cid, int burst_mode, void __iomem *base);
133 int cid, int burst_mode, void __iomem *base);
163 int cid, int burst_mode, void __iomem *base)
171 base + SIRFSOC_DMA_CH_CTRL);
174 writel_relaxed(sdesc->xlen, base + SIRFSOC_DMA_CH_XLEN);
175 writel_relaxed(sdesc->ylen, base + SIRFSOC_DMA_CH_YLEN);
176 writel_relaxed(sdesc->width, base + SIRFSOC_DMA_WIDTH_ATLAS7);
178 base + SIRFSOC_DMA_MUL_ATLAS7);
182 0x3, base + SIRFSOC_DMA_CH_CTRL);
187 base + SIRFSOC_DMA_INT_EN_ATLAS7);
188 writel(sdesc->addr, base + SIRFSOC_DMA_CH_ADDR);
190 writel(0x10001, base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7);
194 int cid, int burst_mode, void __iomem *base)
196 writel_relaxed(1, base + SIRFSOC_DMA_IOBG_SCMD_EN);
197 writel_relaxed((1 << cid), base + SIRFSOC_DMA_EARLY_RESP_SET);
198 writel_relaxed(sdesc->width, base + SIRFSOC_DMA_WIDTH_0 + cid * 4);
201 base + cid * 0x10 + SIRFSOC_DMA_CH_CTRL);
202 writel_relaxed(sdesc->xlen, base + cid * 0x10 + SIRFSOC_DMA_CH_XLEN);
203 writel_relaxed(sdesc->ylen, base + cid * 0x10 + SIRFSOC_DMA_CH_YLEN);
204 writel_relaxed(readl_relaxed(base + SIRFSOC_DMA_INT_EN) |
205 (1 << cid), base + SIRFSOC_DMA_INT_EN);
206 writel(sdesc->addr >> 2, base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR);
209 readl_relaxed(base + SIRFSOC_DMA_CH_LOOP_CTRL_ATLAS7),
210 base + SIRFSOC_DMA_CH_LOOP_CTRL_ATLAS7);
216 int cid, int burst_mode, void __iomem *base)
218 writel_relaxed(sdesc->width, base + SIRFSOC_DMA_WIDTH_0 + cid * 4);
221 base + cid * 0x10 + SIRFSOC_DMA_CH_CTRL);
222 writel_relaxed(sdesc->xlen, base + cid * 0x10 + SIRFSOC_DMA_CH_XLEN);
223 writel_relaxed(sdesc->ylen, base + cid * 0x10 + SIRFSOC_DMA_CH_YLEN);
224 writel_relaxed(readl_relaxed(base + SIRFSOC_DMA_INT_EN) |
225 (1 << cid), base + SIRFSOC_DMA_INT_EN);
226 writel(sdesc->addr >> 2, base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR);
229 readl_relaxed(base + SIRFSOC_DMA_CH_LOOP_CTRL),
230 base + SIRFSOC_DMA_CH_LOOP_CTRL);
241 void __iomem *base;
247 base = sdma->base;
257 sdma->exec_desc(sdesc, cid, schan->mode, base);
277 is = readl(sdma->base + SIRFSOC_DMA_CH_INT);
278 reg = sdma->base + SIRFSOC_DMA_CH_INT;
300 is = readl(sdma->base + SIRFSOC_DMA_INT_ATLAS7);
302 reg = sdma->base + SIRFSOC_DMA_INT_ATLAS7;
453 writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_INT_EN_CLR);
454 writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_INT);
456 sdma->base +
458 writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_VALID);
461 writel_relaxed(0, sdma->base + SIRFSOC_DMA_INT_EN_ATLAS7);
463 sdma->base + SIRFSOC_DMA_INT_ATLAS7);
464 writel_relaxed(0, sdma->base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7);
465 writel_relaxed(0, sdma->base + SIRFSOC_DMA_VALID_ATLAS7);
468 writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) &
469 ~(1 << cid), sdma->base + SIRFSOC_DMA_INT_EN);
470 writel_relaxed(readl_relaxed(sdma->base +
473 sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
474 writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_VALID);
500 sdma->base +
504 writel_relaxed(0, sdma->base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7);
507 writel_relaxed(readl_relaxed(sdma->base +
510 sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
533 sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL_ATLAS7);
537 sdma->base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7);
540 writel_relaxed(readl_relaxed(sdma->base +
543 sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
674 dma_pos = readl_relaxed(sdma->base + SIRFSOC_DMA_CUR_DATA_ADDR);
677 sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR) << 2;
888 sdma->base = devm_ioremap(dev, regs_start, regs_size);
889 if (!sdma->base) {
1045 save->ctrl[ch] = readl_relaxed(sdma->base +
1048 save->interrupt_en = readl_relaxed(sdma->base + int_offset);
1083 writel_relaxed(save->interrupt_en, sdma->base + int_offset);
1092 sdma->base + width_offset + ch * 4);
1094 sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_XLEN);
1096 sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_YLEN);
1098 sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_CTRL);
1101 sdma->base + SIRFSOC_DMA_CH_ADDR);
1104 sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_ADDR);