Lines Matching refs:size
32 * @size: transfer size in bytes
39 u32 size;
59 * @xfer_shift: log2 of the transfer size
68 * @hwdescs.size: size of the hardware descriptors in bytes
69 * @size: transfer size in bytes
87 size_t size;
90 unsigned int size;
121 * @xfer_size: size (in bytes) of hardware transfers
146 * @src: slave memory address and size on the source side
147 * @dst: slave memory address and size on the destination side
296 /* Hardcode the MEMCPY transfer size to 4 bytes. */
422 chan->index, chunk, chunk->size, &chunk->src_addr,
436 chunk->size >> desc->xfer_shift);
697 struct rcar_dmac_desc *desc, size_t size)
700 * dma_alloc_coherent() allocates memory in page size increments. To
701 * avoid reallocating the hardware descriptors when the allocated size
702 * wouldn't change align the requested size to a multiple of the page
703 * size.
705 size = PAGE_ALIGN(size);
707 if (desc->hwdescs.size == size)
711 dma_free_coherent(chan->chan.device->dev, desc->hwdescs.size,
714 desc->hwdescs.size = 0;
717 if (!size)
720 desc->hwdescs.mem = dma_alloc_coherent(chan->chan.device->dev, size,
725 desc->hwdescs.size = size;
743 hwdesc->tcr = chunk->size >> desc->xfer_shift;
954 unsigned int size = min(len, max_chunk_size);
961 if (dev_addr >> 32 != (dev_addr + size - 1) >> 32) {
962 size = ALIGN(dev_addr, 1ULL << 32) - dev_addr;
965 if (mem_addr >> 32 != (mem_addr + size - 1) >> 32) {
966 size = ALIGN(mem_addr, 1ULL << 32) - mem_addr;
985 chunk->size = size;
989 chan->index, chunk, desc, i, sg, size, len,
992 mem_addr += size;
994 dev_addr += size;
996 len -= size;
1004 desc->size = full_size;
1317 * equal to the full descriptor size.
1331 return desc->size;
1335 return desc->size;
1381 /* Compute the size of all chunks still to be transferred. */
1386 residue += chunk->size;
1942 * Default transfer size of 32 bytes requires 32-byte alignment.