Lines Matching defs:s3cdma
261 struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
262 const struct s3c24xx_dma_platdata *pdata = s3cdma->pdata;
271 if (s3cdma->sdata->has_reqsel)
288 struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
294 for (i = 0; i < s3cdma->pdata->num_phy_channels; i++) {
295 phy = &s3cdma->phy_chans[i];
315 if (i == s3cdma->pdata->num_phy_channels) {
316 dev_warn(&s3cdma->pdev->dev, "no phy channel available\n");
321 if (s3cdma->sdata->has_clocks) {
324 dev_err(&s3cdma->pdev->dev, "could not enable clock for channel %d, err %d\n",
341 struct s3c24xx_dma_engine *s3cdma = phy->host;
343 if (s3cdma->sdata->has_clocks)
442 struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
444 const struct s3c24xx_dma_platdata *pdata = s3cdma->pdata;
466 if (s3cdma->sdata->has_reqsel) {
479 if (s3cdma->sdata->has_reqsel)
529 struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
534 dev_dbg(&s3cdma->pdev->dev, "no physical channel available for xfer on %s\n",
540 dev_dbg(&s3cdma->pdev->dev, "allocated physical channel %d for xfer on %s\n",
552 struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
554 dev_dbg(&s3cdma->pdev->dev, "reassigned physical channel %d for xfer on %s\n",
574 struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
581 list_for_each_entry(p, &s3cdma->memcpy.channels, vc.chan.device_node)
588 list_for_each_entry(p, &s3cdma->slave.channels,
702 struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
710 dev_err(&s3cdma->pdev->dev, "trying to terminate already stopped channel %d\n",
820 struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
825 dev_dbg(&s3cdma->pdev->dev, "prepare memcpy of %zu bytes from %s\n",
829 dev_err(&s3cdma->pdev->dev, "memcpy size %zu to large\n", len);
882 struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
883 const struct s3c24xx_dma_platdata *pdata = s3cdma->pdata;
892 dev_dbg(&s3cdma->pdev->dev,
897 dev_err(&s3cdma->pdev->dev,
980 struct s3c24xx_dma_engine *s3cdma = s3cchan->host;
981 const struct s3c24xx_dma_platdata *pdata = s3cdma->pdata;
990 dev_dbg(&s3cdma->pdev->dev, "prepare transaction of %d bytes from %s\n",
1037 dev_err(&s3cdma->pdev->dev,
1088 static int s3c24xx_dma_init_virtual_channels(struct s3c24xx_dma_engine *s3cdma,
1107 chan->host = s3cdma;
1188 struct s3c24xx_dma_engine *s3cdma;
1210 s3cdma = devm_kzalloc(&pdev->dev, sizeof(*s3cdma), GFP_KERNEL);
1211 if (!s3cdma)
1214 s3cdma->pdev = pdev;
1215 s3cdma->pdata = pdata;
1216 s3cdma->sdata = sdata;
1219 s3cdma->base = devm_ioremap_resource(&pdev->dev, res);
1220 if (IS_ERR(s3cdma->base))
1221 return PTR_ERR(s3cdma->base);
1223 s3cdma->phy_chans = devm_kcalloc(&pdev->dev,
1227 if (!s3cdma->phy_chans)
1232 struct s3c24xx_dma_phy *phy = &s3cdma->phy_chans[i];
1236 phy->base = s3cdma->base + (i * sdata->stride);
1237 phy->host = s3cdma;
1276 dma_cap_set(DMA_MEMCPY, s3cdma->memcpy.cap_mask);
1277 dma_cap_set(DMA_PRIVATE, s3cdma->memcpy.cap_mask);
1278 s3cdma->memcpy.dev = &pdev->dev;
1279 s3cdma->memcpy.device_free_chan_resources =
1281 s3cdma->memcpy.device_prep_dma_memcpy = s3c24xx_dma_prep_memcpy;
1282 s3cdma->memcpy.device_tx_status = s3c24xx_dma_tx_status;
1283 s3cdma->memcpy.device_issue_pending = s3c24xx_dma_issue_pending;
1284 s3cdma->memcpy.device_config = s3c24xx_dma_set_runtime_config;
1285 s3cdma->memcpy.device_terminate_all = s3c24xx_dma_terminate_all;
1286 s3cdma->memcpy.device_synchronize = s3c24xx_dma_synchronize;
1289 dma_cap_set(DMA_SLAVE, s3cdma->slave.cap_mask);
1290 dma_cap_set(DMA_CYCLIC, s3cdma->slave.cap_mask);
1291 dma_cap_set(DMA_PRIVATE, s3cdma->slave.cap_mask);
1292 s3cdma->slave.dev = &pdev->dev;
1293 s3cdma->slave.device_free_chan_resources =
1295 s3cdma->slave.device_tx_status = s3c24xx_dma_tx_status;
1296 s3cdma->slave.device_issue_pending = s3c24xx_dma_issue_pending;
1297 s3cdma->slave.device_prep_slave_sg = s3c24xx_dma_prep_slave_sg;
1298 s3cdma->slave.device_prep_dma_cyclic = s3c24xx_dma_prep_dma_cyclic;
1299 s3cdma->slave.device_config = s3c24xx_dma_set_runtime_config;
1300 s3cdma->slave.device_terminate_all = s3c24xx_dma_terminate_all;
1301 s3cdma->slave.device_synchronize = s3c24xx_dma_synchronize;
1302 s3cdma->slave.filter.map = pdata->slave_map;
1303 s3cdma->slave.filter.mapcnt = pdata->slavecnt;
1304 s3cdma->slave.filter.fn = s3c24xx_dma_filter;
1307 ret = s3c24xx_dma_init_virtual_channels(s3cdma, &s3cdma->memcpy,
1317 ret = s3c24xx_dma_init_virtual_channels(s3cdma, &s3cdma->slave,
1326 ret = dma_async_device_register(&s3cdma->memcpy);
1334 ret = dma_async_device_register(&s3cdma->slave);
1342 platform_set_drvdata(pdev, s3cdma);
1349 dma_async_device_unregister(&s3cdma->memcpy);
1351 s3c24xx_dma_free_virtual_channels(&s3cdma->slave);
1353 s3c24xx_dma_free_virtual_channels(&s3cdma->memcpy);
1357 struct s3c24xx_dma_phy *phy = &s3cdma->phy_chans[i];
1366 struct s3c24xx_dma_engine *s3cdma)
1370 for (i = 0; i < s3cdma->pdata->num_phy_channels; i++) {
1371 struct s3c24xx_dma_phy *phy = &s3cdma->phy_chans[i];
1380 struct s3c24xx_dma_engine *s3cdma = platform_get_drvdata(pdev);
1384 dma_async_device_unregister(&s3cdma->slave);
1385 dma_async_device_unregister(&s3cdma->memcpy);
1387 s3c24xx_dma_free_irq(pdev, s3cdma);
1389 s3c24xx_dma_free_virtual_channels(&s3cdma->slave);
1390 s3c24xx_dma_free_virtual_channels(&s3cdma->memcpy);
1394 struct s3c24xx_dma_phy *phy = &s3cdma->phy_chans[i];