Lines Matching refs:val
68 u32 val;
120 val = readl(mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
121 val &= ~(HIDMA_MAX_BUS_REQ_LEN_MASK << HIDMA_MAX_BUS_WR_REQ_BIT_POS);
122 val |= mgmtdev->max_write_request << HIDMA_MAX_BUS_WR_REQ_BIT_POS;
123 val &= ~HIDMA_MAX_BUS_REQ_LEN_MASK;
124 val |= mgmtdev->max_read_request;
125 writel(val, mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
127 val = readl(mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
128 val &= ~(HIDMA_MAX_WR_XACTIONS_MASK << HIDMA_MAX_WR_XACTIONS_BIT_POS);
129 val |= mgmtdev->max_wr_xactions << HIDMA_MAX_WR_XACTIONS_BIT_POS;
130 val &= ~HIDMA_MAX_RD_XACTIONS_MASK;
131 val |= mgmtdev->max_rd_xactions;
132 writel(val, mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
143 val = readl(mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
144 val &= ~(1 << HIDMA_PRIORITY_BIT_POS);
145 val |= (priority & 0x1) << HIDMA_PRIORITY_BIT_POS;
146 val &= ~(HIDMA_WEIGHT_MASK << HIDMA_WRR_BIT_POS);
147 val |= (weight & HIDMA_WEIGHT_MASK) << HIDMA_WRR_BIT_POS;
148 writel(val, mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
151 val = readl(mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
152 val &= ~HIDMA_CHRESET_TIMEOUT_MASK;
153 val |= mgmtdev->chreset_timeout_cycles & HIDMA_CHRESET_TIMEOUT_MASK;
154 writel(val, mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
169 u32 val;
296 val = readl(mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
297 val |= 1;
298 writel(val, mgmtdev->virtaddr + HIDMA_CFG_OFFSET);