Lines Matching defs:mgmtdev
65 int hidma_mgmt_setup(struct hidma_mgmt_dev *mgmtdev)
70 if (!is_power_of_2(mgmtdev->max_write_request) ||
71 (mgmtdev->max_write_request < 128) ||
72 (mgmtdev->max_write_request > 1024)) {
73 dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n",
74 mgmtdev->max_write_request);
78 if (!is_power_of_2(mgmtdev->max_read_request) ||
79 (mgmtdev->max_read_request < 128) ||
80 (mgmtdev->max_read_request > 1024)) {
81 dev_err(&mgmtdev->pdev->dev, "invalid read request %d\n",
82 mgmtdev->max_read_request);
86 if (mgmtdev->max_wr_xactions > HIDMA_MAX_WR_XACTIONS_MASK) {
87 dev_err(&mgmtdev->pdev->dev,
93 if (mgmtdev->max_rd_xactions > HIDMA_MAX_RD_XACTIONS_MASK) {
94 dev_err(&mgmtdev->pdev->dev,
100 for (i = 0; i < mgmtdev->dma_channels; i++) {
101 if (mgmtdev->priority[i] > 1) {
102 dev_err(&mgmtdev->pdev->dev,
107 if (mgmtdev->weight[i] > HIDMA_MAX_CHANNEL_WEIGHT) {
108 dev_err(&mgmtdev->pdev->dev,
115 if (mgmtdev->weight[i] == 0)
116 mgmtdev->weight[i] = 1;
119 pm_runtime_get_sync(&mgmtdev->pdev->dev);
120 val = readl(mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
122 val |= mgmtdev->max_write_request << HIDMA_MAX_BUS_WR_REQ_BIT_POS;
124 val |= mgmtdev->max_read_request;
125 writel(val, mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
127 val = readl(mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
129 val |= mgmtdev->max_wr_xactions << HIDMA_MAX_WR_XACTIONS_BIT_POS;
131 val |= mgmtdev->max_rd_xactions;
132 writel(val, mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
134 mgmtdev->hw_version =
135 readl(mgmtdev->virtaddr + HIDMA_HW_VERSION_OFFSET);
136 mgmtdev->hw_version_major = (mgmtdev->hw_version >> 28) & 0xF;
137 mgmtdev->hw_version_minor = (mgmtdev->hw_version >> 16) & 0xF;
139 for (i = 0; i < mgmtdev->dma_channels; i++) {
140 u32 weight = mgmtdev->weight[i];
141 u32 priority = mgmtdev->priority[i];
143 val = readl(mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
148 writel(val, mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
151 val = readl(mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
153 val |= mgmtdev->chreset_timeout_cycles & HIDMA_CHRESET_TIMEOUT_MASK;
154 writel(val, mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
156 pm_runtime_mark_last_busy(&mgmtdev->pdev->dev);
157 pm_runtime_put_autosuspend(&mgmtdev->pdev->dev);
164 struct hidma_mgmt_dev *mgmtdev;
190 mgmtdev = devm_kzalloc(&pdev->dev, sizeof(*mgmtdev), GFP_KERNEL);
191 if (!mgmtdev) {
196 mgmtdev->pdev = pdev;
197 mgmtdev->addrsize = resource_size(res);
198 mgmtdev->virtaddr = virtaddr;
201 &mgmtdev->dma_channels);
209 &mgmtdev->chreset_timeout_cycles);
216 &mgmtdev->max_write_request);
223 (max_write_request != mgmtdev->max_write_request)) {
226 mgmtdev->max_write_request = max_write_request;
228 max_write_request = mgmtdev->max_write_request;
231 &mgmtdev->max_read_request);
237 (max_read_request != mgmtdev->max_read_request)) {
240 mgmtdev->max_read_request = max_read_request;
242 max_read_request = mgmtdev->max_read_request;
245 &mgmtdev->max_wr_xactions);
251 (max_wr_xactions != mgmtdev->max_wr_xactions)) {
254 mgmtdev->max_wr_xactions = max_wr_xactions;
256 max_wr_xactions = mgmtdev->max_wr_xactions;
259 &mgmtdev->max_rd_xactions);
265 (max_rd_xactions != mgmtdev->max_rd_xactions)) {
268 mgmtdev->max_rd_xactions = max_rd_xactions;
270 max_rd_xactions = mgmtdev->max_rd_xactions;
272 mgmtdev->priority = devm_kcalloc(&pdev->dev,
273 mgmtdev->dma_channels,
274 sizeof(*mgmtdev->priority),
276 if (!mgmtdev->priority) {
281 mgmtdev->weight = devm_kcalloc(&pdev->dev,
282 mgmtdev->dma_channels,
283 sizeof(*mgmtdev->weight), GFP_KERNEL);
284 if (!mgmtdev->weight) {
289 rc = hidma_mgmt_setup(mgmtdev);
296 val = readl(mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
298 writel(val, mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
300 rc = hidma_mgmt_init_sys(mgmtdev);
308 mgmtdev->hw_version_major, mgmtdev->hw_version_minor,
309 &res->start, mgmtdev->dma_channels);
311 platform_set_drvdata(pdev, mgmtdev);