Lines Matching refs:evca
244 evre_write_off = readl_relaxed(lldev->evca + HIDMA_EVCA_WRITE_PTR_REG);
279 readl_relaxed(lldev->evca + HIDMA_EVCA_WRITE_PTR_REG);
294 writel(evre_read_off, lldev->evca + HIDMA_EVCA_DOORBELL_REG);
334 val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG);
337 writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG);
343 ret = readl_poll_timeout(lldev->evca + HIDMA_EVCA_CTRLSTS_REG, val,
395 writel(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
408 writel_relaxed(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
431 status = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);
432 enable = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
442 status = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);
443 enable = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
463 val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG);
466 writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG);
468 ret = readl_poll_timeout(lldev->evca + HIDMA_EVCA_CTRLSTS_REG, val,
493 writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
513 val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG);
575 val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG);
578 writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG);
584 ret = readl_poll_timeout(lldev->evca + HIDMA_EVCA_CTRLSTS_REG, val,
594 writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
646 writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
649 val = readl(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);
650 writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
660 val = readl(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);
661 writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
664 writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
672 writel(lower_32_bits(addr), lldev->evca + HIDMA_EVCA_RING_LOW_REG);
673 writel(upper_32_bits(addr), lldev->evca + HIDMA_EVCA_RING_HIGH_REG);
675 lldev->evca + HIDMA_EVCA_RING_LEN_REG);
694 writel(0, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
695 writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
698 val = readl(lldev->evca + HIDMA_EVCA_INTCTRL_REG);
702 writel(val, lldev->evca + HIDMA_EVCA_INTCTRL_REG);
705 writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
706 writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
710 void __iomem *trca, void __iomem *evca,
718 if (!trca || !evca || !dev || !nr_tres)
732 lldev->evca = evca;
797 writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
828 val = readl(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);
829 writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
830 writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);