Lines Matching refs:chan
67 struct dma_chan *chan;
129 static void print_cb(struct ppc440spe_adma_chan *chan, void *block)
135 switch (chan->device->id) {
145 cdb, chan->device->id,
159 cb, chan->device->id,
173 static void print_cb_list(struct ppc440spe_adma_chan *chan,
177 print_cb(chan, iter->hw_desc);
232 struct ppc440spe_adma_chan *chan)
236 switch (chan->device->id) {
250 printk(KERN_ERR "Unsupported id %d in %s\n", chan->device->id,
442 * and/or Q to chan->pdest and/or chan->qdest as we have
523 struct ppc440spe_adma_chan *chan,
531 switch (chan->device->id) {
558 struct ppc440spe_adma_chan *chan, u32 mult_index,
565 switch (chan->device->id) {
604 struct ppc440spe_adma_chan *chan,
613 switch (chan->device->id) {
645 struct ppc440spe_adma_chan *chan,
651 switch (chan->device->id) {
680 struct ppc440spe_adma_chan *chan, u8 *qword)
684 switch (chan->device->id) {
723 static void ppc440spe_desc_set_link(struct ppc440spe_adma_chan *chan,
747 switch (chan->device->id) {
772 struct ppc440spe_adma_chan *chan)
892 ppc440spe_chan_get_current_descriptor(struct ppc440spe_adma_chan *chan);
893 static void ppc440spe_chan_append(struct ppc440spe_adma_chan *chan);
899 struct ppc440spe_adma_chan *chan)
903 u8 *p = chan->device->dma_desc_pool_virt;
907 switch (chan->device->id) {
911 dma_reg = chan->device->dma_reg;
915 (u32)chan->device->dma_desc_pool];
947 list_for_each_entry(iter, &chan->chain,
956 BUG_ON(&iter->chain_node == &chan->chain);
977 chan->device->id, rv);
984 xor_reg = chan->device->xor_reg;
1010 ppc440spe_chan_append(chan);
1018 static int ppc440spe_chan_is_busy(struct ppc440spe_adma_chan *chan)
1024 switch (chan->device->id) {
1027 dma_reg = chan->device->dma_reg;
1038 xor_reg = chan->device->xor_reg;
1050 struct ppc440spe_adma_chan *chan,
1053 struct xor_regs *xor_reg = chan->device->xor_reg;
1069 chan->hw_chain_inited = 1;
1076 static void ppc440spe_dma_put_desc(struct ppc440spe_adma_chan *chan,
1080 struct dma_regs *dma_reg = chan->device->dma_reg;
1086 chan_last_sub[chan->device->id] = desc;
1088 ADMA_LL_DBG(print_cb(chan, desc->hw_desc));
1096 static void ppc440spe_chan_append(struct ppc440spe_adma_chan *chan)
1106 switch (chan->device->id) {
1109 cur_desc = ppc440spe_chan_get_current_descriptor(chan);
1112 iter = chan_last_sub[chan->device->id];
1116 iter = chan_first_cdb[chan->device->id];
1118 ppc440spe_dma_put_desc(chan, iter);
1119 chan->hw_chain_inited = 1;
1127 list_for_each_entry_continue(iter, &chan->chain, chain_node) {
1128 ppc440spe_dma_put_desc(chan, iter);
1138 xor_reg = chan->device->xor_reg;
1153 ADMA_LL_DBG(print_cb_list(chan,
1175 ppc440spe_chan_get_current_descriptor(struct ppc440spe_adma_chan *chan)
1180 if (unlikely(!chan->hw_chain_inited))
1184 switch (chan->device->id) {
1187 dma_reg = chan->device->dma_reg;
1190 xor_reg = chan->device->xor_reg;
1199 static void ppc440spe_chan_run(struct ppc440spe_adma_chan *chan)
1203 switch (chan->device->id) {
1210 xor_reg = chan->device->xor_reg;
1223 static void ppc440spe_chan_start_null_xor(struct ppc440spe_adma_chan *chan);
1224 static int ppc440spe_adma_alloc_chan_resources(struct dma_chan *chan);
1318 * the operation given on this channel. It's assumed that 'chan' is
1320 * @chan: channel to use
1328 static int ppc440spe_adma_estimate(struct dma_chan *chan,
1351 if (cap == DMA_PQ && chan->chan_id == PPC440SPE_XOR_ID) {
1363 !ppc440spe_chan_is_busy(to_ppc440spe_adma_chan(chan)))
1402 if (dma_has_cap(cap, ref->chan->device->cap_mask)) {
1405 rank = ppc440spe_adma_estimate(ref->chan, cap, dst_lst,
1409 best_chan = ref->chan;
1447 struct ppc440spe_adma_chan *chan)
1465 struct ppc440spe_adma_chan *chan,
1490 struct ppc440spe_adma_chan *chan)
1501 if (list_is_last(&desc->chain_node, &chan->chain) ||
1502 desc->phys == ppc440spe_chan_get_current_descriptor(chan))
1505 if (chan->device->id != PPC440SPE_XOR_ID) {
1520 dev_dbg(chan->device->common.dev, "\tfree slot %llx: %d stride: %d\n",
1524 ppc440spe_adma_free_slots(desc, chan);
1535 static void __ppc440spe_adma_slot_cleanup(struct ppc440spe_adma_chan *chan)
1539 u32 current_desc = ppc440spe_chan_get_current_descriptor(chan);
1540 int busy = ppc440spe_chan_is_busy(chan);
1543 dev_dbg(chan->device->common.dev, "ppc440spe adma%d: %s\n",
1544 chan->device->id, __func__);
1556 list_for_each_entry_safe(iter, _iter, &chan->chain,
1558 dev_dbg(chan->device->common.dev, "\tcookie: %d slot: %d "
1562 ppc440spe_desc_get_link(iter, chan), current_desc,
1580 if (busy || ppc440spe_desc_get_link(iter, chan)) {
1613 &chan->chain, chain_node) {
1616 grp_iter, chan, cookie);
1620 grp_iter, chan);
1624 chan->common.completed_cookie = cookie;
1644 cookie = ppc440spe_adma_run_tx_complete_actions(iter, chan,
1647 if (ppc440spe_adma_clean_slot(iter, chan))
1654 chan->common.completed_cookie = cookie;
1665 struct ppc440spe_adma_chan *chan = from_tasklet(chan, t, irq_tasklet);
1667 spin_lock_nested(&chan->lock, SINGLE_DEPTH_NESTING);
1668 __ppc440spe_adma_slot_cleanup(chan);
1669 spin_unlock(&chan->lock);
1675 static void ppc440spe_adma_slot_cleanup(struct ppc440spe_adma_chan *chan)
1677 spin_lock_bh(&chan->lock);
1678 __ppc440spe_adma_slot_cleanup(chan);
1679 spin_unlock_bh(&chan->lock);
1686 struct ppc440spe_adma_chan *chan, int num_slots,
1703 iter = chan->last_used;
1705 iter = list_entry(&chan->all_slots,
1708 list_for_each_entry_safe_continue(iter, _iter, &chan->all_slots,
1751 chan->last_used = last_used;
1759 tasklet_schedule(&chan->irq_tasklet);
1766 static int ppc440spe_adma_alloc_chan_resources(struct dma_chan *chan)
1774 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
1776 chan->chan_id = ppc440spe_chan->device->id;
1796 dma_async_tx_descriptor_init(&slot->async_tx, chan);
1881 static void ppc440spe_adma_check_threshold(struct ppc440spe_adma_chan *chan)
1883 dev_dbg(chan->device->common.dev, "ppc440spe adma%d: pending: %d\n",
1884 chan->device->id, chan->pending);
1886 if (chan->pending >= PPC440SPE_ADMA_THRESHOLD) {
1887 chan->pending = 0;
1888 ppc440spe_chan_append(chan);
1900 struct ppc440spe_adma_chan *chan = to_ppc440spe_adma_chan(tx->chan);
1912 spin_lock_bh(&chan->lock);
1915 if (unlikely(list_empty(&chan->chain))) {
1917 list_splice_init(&sw_desc->group_list, &chan->chain);
1918 chan_first_cdb[chan->device->id] = group_start;
1921 old_chain_tail = list_entry(chan->chain.prev,
1927 ppc440spe_desc_set_link(chan, old_chain_tail, group_start);
1931 chan->pending += slot_cnt / slots_per_op;
1932 ppc440spe_adma_check_threshold(chan);
1933 spin_unlock_bh(&chan->lock);
1935 dev_dbg(chan->device->common.dev,
1937 chan->device->id, __func__,
1947 struct dma_chan *chan, unsigned long flags)
1953 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
1978 struct dma_chan *chan, dma_addr_t dma_dest,
1985 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
2019 struct dma_chan *chan, dma_addr_t dma_dest,
2027 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
2102 struct ppc440spe_adma_chan *chan;
2106 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
2125 ppc440spe_desc_set_dest_addr(iter, chan,
2127 ppc440spe_desc_set_dest_addr(iter, chan, 0, dst[1], 1);
2128 ppc440spe_desc_set_src_addr(iter, chan, 0, DMA_CUED_XOR_HB,
2149 ppc440spe_desc_set_src_addr(iter, chan, 0,
2151 ppc440spe_desc_set_dest_addr(iter, chan,
2154 ppc440spe_desc_set_src_mult(iter, chan, DMA_CUED_MULT1_OFF,
2188 struct ppc440spe_adma_chan *chan;
2192 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
2208 ppc440spe_desc_set_dest_addr(iter, chan, DMA_CUED_XOR_BASE,
2210 ppc440spe_desc_set_dest_addr(iter, chan, 0,
2212 ppc440spe_desc_set_src_addr(iter, chan, 0, DMA_CUED_XOR_HB,
2234 ppc440spe_desc_set_src_addr(iter, chan, 0, DMA_CUED_XOR_HB,
2236 ppc440spe_desc_set_dest_addr(iter, chan, DMA_CUED_XOR_BASE,
2238 ppc440spe_desc_set_src_mult(iter, chan, DMA_CUED_MULT1_OFF,
2259 ppc440spe_desc_set_src_addr(iter, chan, 0, DMA_CUED_XOR_HB,
2261 ppc440spe_desc_set_dest_addr(iter, chan, DMA_CUED_XOR_BASE,
2263 ppc440spe_desc_set_src_mult(iter, chan, DMA_CUED_MULT1_OFF,
2510 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
2518 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
2586 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
2595 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
2637 struct ppc440spe_adma_chan *chan;
2640 chan = to_ppc440spe_adma_chan(iter->async_tx.chan);
2649 ppc440spe_desc_set_dest_addr(iter, chan, 0,
2651 ppc440spe_desc_set_src_addr(iter, chan, 0, 0, pdest);
2660 struct ppc440spe_adma_chan *chan;
2665 chan = to_ppc440spe_adma_chan(iter->async_tx.chan);
2681 ppc440spe_desc_set_dest_addr(iter, chan, 0,
2683 ppc440spe_desc_set_src_addr(iter, chan, 0, 0, qdest);
2737 struct ppc440spe_adma_chan *chan;
2740 chan = to_ppc440spe_adma_chan(iter->async_tx.chan);
2741 ppc440spe_desc_set_src_addr(iter, chan, 0,
2747 ppc440spe_desc_set_src_mult(iter, chan,
2765 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
2776 tx = ppc440spe_adma_prep_dma_pqzero_sum(chan, pq, &src[1],
2788 struct ppc440spe_adma_chan *chan;
2792 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
2794 switch (chan->device->id) {
2801 chan, 0, addr, index);
2806 chan, 0, addr, index);
2812 struct ppc440spe_adma_chan *chan, dma_addr_t addr)
2818 ppc440spe_desc_set_dest_addr(iter, chan, DMA_CUED_XOR_BASE, addr, 0);
2821 ppc440spe_desc_set_src_addr(iter, chan, 0, DMA_CUED_XOR_HB, addr);
2824 ppc440spe_desc_set_src_mult(iter, chan, DMA_CUED_MULT1_OFF,
2836 struct ppc440spe_adma_chan *chan;
2841 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
2856 switch (chan->device->id) {
2874 ppc440spe_desc_set_dest_addr(iter, chan,
2880 ppc440spe_desc_set_dest_addr(iter, chan,
2882 ppc440spe_desc_set_dest_addr(iter, chan,
2896 ppc440spe_adma_pq_zero_op(iter, chan,
2904 ppc440spe_adma_pq_zero_op(iter, chan,
2927 ppc440spe_desc_set_dest_addr(iter, chan,
2934 ppc440spe_desc_set_dest_addr(iter, chan,
2950 iter, chan,
2960 iter, chan,
2964 iter, chan,
2992 ppc440spe_desc_set_dest_addr(iter, chan,
3006 chan, qpath, qaddr, 0);
3026 struct ppc440spe_adma_chan *chan;
3030 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3052 ppc440spe_desc_set_dest_addr(iter, chan,
3054 ppc440spe_desc_set_dest_addr(iter, chan,
3064 ppc440spe_desc_set_dest_addr(iter, chan,
3073 ppc440spe_desc_set_src_addr(end, chan, 0, 0, addr ? addr : paddr);
3078 ppc440spe_desc_set_src_addr(end, chan, 0, 0, qaddr);
3101 struct ppc440spe_adma_chan *chan;
3105 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3107 switch (chan->device->id) {
3173 ppc440spe_desc_set_src_addr(iter, chan, 0, haddr, addr);
3182 ppc440spe_desc_set_src_addr(iter, chan, 0,
3211 struct ppc440spe_adma_chan *chan;
3213 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3217 ppc440spe_desc_set_src_addr(sw_desc, chan, index, 0, addr);
3453 struct ppc440spe_adma_chan *chan;
3457 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3459 switch (chan->device->id) {
3503 ppc440spe_desc_set_src_mult(iter, chan,
3510 ppc440spe_desc_set_src_mult(iter1, chan,
3535 static void ppc440spe_adma_free_chan_resources(struct dma_chan *chan)
3541 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
3572 * @chan: ADMA channel handle
3576 static enum dma_status ppc440spe_adma_tx_status(struct dma_chan *chan,
3582 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
3583 ret = dma_cookie_status(chan, cookie, txstate);
3589 return dma_cookie_status(chan, cookie, txstate);
3597 struct ppc440spe_adma_chan *chan = data;
3599 dev_dbg(chan->device->common.dev,
3600 "ppc440spe adma%d: %s\n", chan->device->id, __func__);
3602 tasklet_schedule(&chan->irq_tasklet);
3603 ppc440spe_adma_device_clear_eot_status(chan);
3614 struct ppc440spe_adma_chan *chan = data;
3616 dev_dbg(chan->device->common.dev,
3617 "ppc440spe adma%d: %s\n", chan->device->id, __func__);
3619 tasklet_schedule(&chan->irq_tasklet);
3620 ppc440spe_adma_device_clear_eot_status(chan);
3636 static void ppc440spe_adma_issue_pending(struct dma_chan *chan)
3640 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
3656 static void ppc440spe_chan_start_null_xor(struct ppc440spe_adma_chan *chan)
3662 dev_dbg(chan->device->common.dev,
3663 "ppc440spe adma%d: %s\n", chan->device->id, __func__);
3665 spin_lock_bh(&chan->lock);
3667 sw_desc = ppc440spe_adma_alloc_slots(chan, slot_cnt, slots_per_op);
3670 list_splice_init(&sw_desc->group_list, &chan->chain);
3679 chan->common.completed_cookie = cookie - 1;
3682 BUG_ON(ppc440spe_chan_is_busy(chan));
3685 ppc440spe_chan_set_first_xor_descriptor(chan, sw_desc);
3688 ppc440spe_chan_run(chan);
3692 chan->device->id);
3693 spin_unlock_bh(&chan->lock);
3702 static int ppc440spe_test_raid6(struct ppc440spe_adma_chan *chan)
3717 spin_lock_bh(&chan->lock);
3718 sw_desc = ppc440spe_adma_alloc_slots(chan, 1, 1);
3723 ppc440spe_desc_set_byte_count(iter, chan, PAGE_SIZE);
3728 spin_unlock_bh(&chan->lock);
3731 spin_unlock_bh(&chan->lock);
3735 dma_addr = dma_map_page(chan->device->dev, pg, 0,
3752 ppc440spe_adma_issue_pending(&chan->common);
3868 struct ppc440spe_adma_chan *chan,
3900 0, dev_driver_string(adev->dev), chan);
3918 chan);
3963 free_irq(adev->irq, chan);
3975 struct ppc440spe_adma_chan *chan)
3993 free_irq(adev->irq, chan);
3996 free_irq(adev->err_irq, chan);
4012 struct ppc440spe_adma_chan *chan;
4130 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
4131 if (!chan) {
4137 spin_lock_init(&chan->lock);
4138 INIT_LIST_HEAD(&chan->chain);
4139 INIT_LIST_HEAD(&chan->all_slots);
4140 chan->device = adev;
4141 chan->common.device = &adev->common;
4142 dma_cookie_init(&chan->common);
4143 list_add_tail(&chan->common.device_node, &adev->common.channels);
4144 tasklet_setup(&chan->irq_tasklet, ppc440spe_adma_tasklet);
4150 chan->pdest_page = alloc_page(GFP_KERNEL);
4151 chan->qdest_page = alloc_page(GFP_KERNEL);
4152 if (!chan->pdest_page ||
4153 !chan->qdest_page) {
4154 if (chan->pdest_page)
4155 __free_page(chan->pdest_page);
4156 if (chan->qdest_page)
4157 __free_page(chan->qdest_page);
4161 chan->pdest = dma_map_page(&ofdev->dev, chan->pdest_page, 0,
4163 chan->qdest = dma_map_page(&ofdev->dev, chan->qdest_page, 0,
4169 ref->chan = &chan->common;
4178 ret = ppc440spe_adma_setup_irqs(adev, chan, &initcode);
4194 ppc440spe_adma_release_irqs(adev, chan);
4197 if (chan == to_ppc440spe_adma_chan(ref->chan)) {
4204 dma_unmap_page(&ofdev->dev, chan->pdest,
4206 dma_unmap_page(&ofdev->dev, chan->qdest,
4208 __free_page(chan->pdest_page);
4209 __free_page(chan->qdest_page);
4212 kfree(chan);
4241 struct dma_chan *chan, *_chan;
4250 list_for_each_entry_safe(chan, _chan, &adev->common.channels,
4252 ppc440spe_chan = to_ppc440spe_adma_chan(chan);
4266 to_ppc440spe_adma_chan(ref->chan)) {
4271 list_del(&chan->device_node);