Lines Matching defs:sw_desc
1899 struct ppc440spe_adma_desc_slot *sw_desc;
1906 sw_desc = tx_to_ppc440spe_adma_slot(tx);
1908 group_start = sw_desc->group_head;
1917 list_splice_init(&sw_desc->group_list, &chan->chain);
1924 list_splice_init(&sw_desc->group_list,
1938 sw_desc->async_tx.cookie, sw_desc->idx, sw_desc);
1950 struct ppc440spe_adma_desc_slot *sw_desc, *group_start;
1961 sw_desc = ppc440spe_adma_alloc_slots(ppc440spe_chan, slot_cnt,
1963 if (sw_desc) {
1964 group_start = sw_desc->group_head;
1967 sw_desc->async_tx.flags = flags;
1971 return sw_desc ? &sw_desc->async_tx : NULL;
1982 struct ppc440spe_adma_desc_slot *sw_desc, *group_start;
1999 sw_desc = ppc440spe_adma_alloc_slots(ppc440spe_chan, slot_cnt,
2001 if (sw_desc) {
2002 group_start = sw_desc->group_head;
2007 sw_desc->unmap_len = len;
2008 sw_desc->async_tx.flags = flags;
2012 return sw_desc ? &sw_desc->async_tx : NULL;
2024 struct ppc440spe_adma_desc_slot *sw_desc, *group_start;
2042 sw_desc = ppc440spe_adma_alloc_slots(ppc440spe_chan, slot_cnt,
2044 if (sw_desc) {
2045 group_start = sw_desc->group_head;
2052 sw_desc->unmap_len = len;
2053 sw_desc->async_tx.flags = flags;
2057 return sw_desc ? &sw_desc->async_tx : NULL;
2090 struct ppc440spe_adma_desc_slot *sw_desc = NULL;
2100 sw_desc = ppc440spe_adma_alloc_slots(ppc440spe_chan, slot_cnt, 1);
2101 if (sw_desc) {
2106 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
2107 set_bits(op, &sw_desc->flags);
2108 sw_desc->src_cnt = src_cnt;
2109 sw_desc->dst_cnt = dst_cnt;
2113 iter = list_first_entry(&sw_desc->group_list,
2158 sw_desc->async_tx.flags = flags;
2163 return sw_desc;
2176 struct ppc440spe_adma_desc_slot *sw_desc = NULL;
2186 sw_desc = ppc440spe_adma_alloc_slots(ppc440spe_chan, slot_cnt, 1);
2187 if (sw_desc) {
2192 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
2193 set_bits(op, &sw_desc->flags);
2194 sw_desc->src_cnt = src_cnt;
2195 sw_desc->dst_cnt = 1;
2197 iter = list_first_entry(&sw_desc->group_list,
2267 sw_desc->async_tx.flags = flags;
2272 return sw_desc;
2281 struct ppc440spe_adma_desc_slot *sw_desc = NULL, *iter;
2381 sw_desc = ppc440spe_adma_alloc_slots(ppc440spe_chan, slot_cnt, 1);
2382 if (sw_desc) {
2383 ppc440spe_desc_init_dma01pq(sw_desc, dst_cnt, src_cnt,
2389 ppc440spe_adma_pq_set_dest(sw_desc, dst, flags);
2391 ppc440spe_adma_pq_set_src(sw_desc, src[src_cnt],
2402 ppc440spe_adma_pq_set_src_mult(sw_desc,
2407 sw_desc->async_tx.flags = flags;
2408 list_for_each_entry(iter, &sw_desc->group_list,
2417 return sw_desc;
2426 struct ppc440spe_adma_desc_slot *sw_desc = NULL, *iter;
2444 sw_desc = ppc440spe_adma_alloc_slots(ppc440spe_chan, slot_cnt, 1);
2445 if (sw_desc) {
2447 sw_desc->async_tx.flags = flags;
2448 list_for_each_entry(iter, &sw_desc->group_list, chain_node) {
2460 list_for_each_entry(iter, &sw_desc->group_list, chain_node) {
2466 &sw_desc->group_list))) {
2480 sw_desc->dst_cnt = dst_cnt;
2482 set_bit(PPC440SPE_ZERO_P, &sw_desc->flags);
2484 set_bit(PPC440SPE_ZERO_Q, &sw_desc->flags);
2487 ppc440spe_adma_pq_set_dest(sw_desc, dst, flags);
2493 ppc440spe_adma_pq_set_src(sw_desc, src[src_cnt],
2497 ppc440spe_adma_pq_set_src_mult(sw_desc,
2503 return sw_desc;
2515 struct ppc440spe_adma_desc_slot *sw_desc = NULL;
2533 sw_desc = ppc440spe_dma01_prep_mult(ppc440spe_chan,
2535 return sw_desc ? &sw_desc->async_tx : NULL;
2539 sw_desc = ppc440spe_dma01_prep_sum_product(ppc440spe_chan,
2541 return sw_desc ? &sw_desc->async_tx : NULL;
2566 sw_desc = ppc440spe_dma01_prep_pq(ppc440spe_chan,
2572 sw_desc = ppc440spe_dma2_prep_pq(ppc440spe_chan,
2578 return sw_desc ? &sw_desc->async_tx : NULL;
2591 struct ppc440spe_adma_desc_slot *sw_desc, *iter;
2622 sw_desc = ppc440spe_adma_alloc_slots(ppc440spe_chan, slot_cnt,
2624 if (sw_desc) {
2625 ppc440spe_desc_init_dma01pqzero_sum(sw_desc, dst_cnt, src_cnt);
2628 sw_desc->async_tx.flags = flags;
2629 list_for_each_entry(iter, &sw_desc->group_list, chain_node) {
2639 iter = sw_desc->group_head;
2662 iter = list_first_entry(&sw_desc->group_list,
2692 ppc440spe_adma_pqzero_sum_set_dest(sw_desc, pdest, qdest);
2696 list_for_each_entry_reverse(iter, &sw_desc->group_list,
2735 list_for_each_entry_continue_reverse(iter, &sw_desc->group_list,
2757 return sw_desc ? &sw_desc->async_tx : NULL;
2785 static void ppc440spe_adma_set_dest(struct ppc440spe_adma_desc_slot *sw_desc,
2790 BUG_ON(index >= sw_desc->dst_cnt);
2792 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
2800 ppc440spe_desc_set_dest_addr(sw_desc->group_head,
2804 sw_desc = ppc440spe_get_group_entry(sw_desc, index);
2805 ppc440spe_desc_set_dest_addr(sw_desc,
2832 static void ppc440spe_adma_pq_set_dest(struct ppc440spe_adma_desc_slot *sw_desc,
2841 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
2862 if (!test_bit(PPC440SPE_DESC_RXOR, &sw_desc->flags)) {
2864 if (test_bit(PPC440SPE_ZERO_P, &sw_desc->flags))
2866 if (test_bit(PPC440SPE_ZERO_Q, &sw_desc->flags))
2869 iter = ppc440spe_get_group_entry(sw_desc, index);
2873 &sw_desc->group_list, chain_node)
2879 &sw_desc->group_list, chain_node) {
2893 &sw_desc->flags)) {
2895 sw_desc, index++);
2901 &sw_desc->flags)) {
2903 sw_desc, index++);
2916 ppath = test_bit(PPC440SPE_ZERO_P, &sw_desc->flags) ?
2920 qpath = test_bit(PPC440SPE_ZERO_Q, &sw_desc->flags) ?
2926 iter = ppc440spe_get_group_entry(sw_desc, index++);
2932 iter = ppc440spe_get_group_entry(sw_desc,
2938 if (test_bit(PPC440SPE_DESC_WXOR, &sw_desc->flags)) {
2942 iter = ppc440spe_get_group_entry(sw_desc,
2947 &sw_desc->group_list,
2957 &sw_desc->group_list,
2980 ppath = test_bit(PPC440SPE_ZERO_P, &sw_desc->flags) ?
2985 qpath = test_bit(PPC440SPE_ZERO_Q, &sw_desc->flags) ?
2990 iter = ppc440spe_get_group_entry(sw_desc, 0);
2991 for (i = 0; i < sw_desc->descs_per_op; i++) {
3002 iter = ppc440spe_get_group_entry(sw_desc,
3003 sw_desc->descs_per_op);
3004 for (i = 0; i < sw_desc->descs_per_op; i++) {
3022 struct ppc440spe_adma_desc_slot *sw_desc,
3030 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3037 list_for_each_entry_reverse(end, &sw_desc->group_list,
3044 iter = ppc440spe_get_group_entry(sw_desc, idx);
3048 list_for_each_entry_from(iter, &sw_desc->group_list,
3060 list_for_each_entry_from(iter, &sw_desc->group_list,
3098 static void ppc440spe_adma_pq_set_src(struct ppc440spe_adma_desc_slot *sw_desc,
3105 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3112 if (test_bit(PPC440SPE_DESC_RXOR, &sw_desc->flags)) {
3115 &sw_desc->flags) ? 2 : 3;
3123 &sw_desc->flags))
3127 &sw_desc->flags))
3131 &sw_desc->flags))
3135 &sw_desc->flags))
3141 iter = ppc440spe_get_group_entry(sw_desc, 0);
3153 iter = ppc440spe_get_group_entry(sw_desc,
3154 index - iskip + sw_desc->dst_cnt);
3162 if (test_bit(PPC440SPE_ZERO_P, &sw_desc->flags))
3164 if (test_bit(PPC440SPE_ZERO_Q, &sw_desc->flags))
3168 iter = ppc440spe_get_group_entry(sw_desc,
3176 test_bit(PPC440SPE_DESC_RXOR, &sw_desc->flags) &&
3177 sw_desc->dst_cnt == 2) {
3181 iter = ppc440spe_get_group_entry(sw_desc, 1);
3190 iter = sw_desc->group_head;
3196 iter = ppc440spe_get_group_entry(sw_desc,
3197 sw_desc->descs_per_op);
3208 struct ppc440spe_adma_desc_slot *sw_desc,
3213 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3214 sw_desc = sw_desc->group_head;
3216 if (likely(sw_desc))
3217 ppc440spe_desc_set_src_addr(sw_desc, chan, index, 0, addr);
3450 struct ppc440spe_adma_desc_slot *sw_desc,
3457 chan = to_ppc440spe_adma_chan(sw_desc->async_tx.chan);
3462 if (test_bit(PPC440SPE_DESC_RXOR, &sw_desc->flags)) {
3464 &sw_desc->flags) ? 2 : 3;
3468 iter = ppc440spe_get_group_entry(sw_desc,
3469 sw_desc->dst_cnt - 1);
3470 if (sw_desc->dst_cnt == 2)
3472 sw_desc, 0);
3478 iter = ppc440spe_get_group_entry(sw_desc,
3480 sw_desc->dst_cnt);
3492 if (test_bit(PPC440SPE_ZERO_P, &sw_desc->flags))
3494 if (test_bit(PPC440SPE_ZERO_Q, &sw_desc->flags))
3497 iter = ppc440spe_get_group_entry(sw_desc, index + znum);
3518 iter = sw_desc->group_head;
3519 if (sw_desc->dst_cnt == 2) {
3524 iter = ppc440spe_get_group_entry(sw_desc,
3525 sw_desc->descs_per_op);
3658 struct ppc440spe_adma_desc_slot *sw_desc, *group_start;
3667 sw_desc = ppc440spe_adma_alloc_slots(chan, slot_cnt, slots_per_op);
3668 if (sw_desc) {
3669 group_start = sw_desc->group_head;
3670 list_splice_init(&sw_desc->group_list, &chan->chain);
3671 async_tx_ack(&sw_desc->async_tx);
3674 cookie = dma_cookie_assign(&sw_desc->async_tx);
3685 ppc440spe_chan_set_first_xor_descriptor(chan, sw_desc);
3704 struct ppc440spe_adma_desc_slot *sw_desc, *iter;
3718 sw_desc = ppc440spe_adma_alloc_slots(chan, 1, 1);
3719 if (sw_desc) {
3721 ppc440spe_desc_init_dma01pq(sw_desc, 1, 1, 1, op);
3722 list_for_each_entry(iter, &sw_desc->group_list, chain_node) {
3739 ppc440spe_adma_pq_set_src(sw_desc, dma_addr, 0);
3740 ppc440spe_adma_pq_set_src_mult(sw_desc, 1, 0, 0);
3743 ppc440spe_adma_pq_set_dest(sw_desc, addrs, DMA_PREP_PQ_DISABLE_Q);
3745 async_tx_ack(&sw_desc->async_tx);
3746 sw_desc->async_tx.callback = ppc440spe_test_callback;
3747 sw_desc->async_tx.callback_param = NULL;
3751 ppc440spe_adma_tx_submit(&sw_desc->async_tx);