Lines Matching refs:mcf_edma
19 struct fsl_edma_engine *mcf_edma = dev_id;
20 struct edma_regs *regs = &mcf_edma->regs;
31 for (ch = 0; ch < mcf_edma->n_chans; ch++) {
35 mcf_chan = &mcf_edma->chans[ch];
67 struct fsl_edma_engine *mcf_edma = dev_id;
68 struct edma_regs *regs = &mcf_edma->regs;
77 fsl_edma_disable_request(&mcf_edma->chans[ch]);
79 mcf_edma->chans[ch].status = DMA_ERROR;
80 mcf_edma->chans[ch].idle = true;
90 fsl_edma_disable_request(&mcf_edma->chans[ch]);
92 mcf_edma->chans[ch].status = DMA_ERROR;
93 mcf_edma->chans[ch].idle = true;
101 struct fsl_edma_engine *mcf_edma)
112 ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
122 ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
129 0, "eDMA", mcf_edma);
137 0, "eDMA", mcf_edma);
146 struct fsl_edma_engine *mcf_edma)
155 free_irq(irq, mcf_edma);
162 free_irq(irq, mcf_edma);
167 free_irq(irq, mcf_edma);
171 free_irq(irq, mcf_edma);
182 struct fsl_edma_engine *mcf_edma;
201 len = sizeof(*mcf_edma) + sizeof(*mcf_chan) * chans;
202 mcf_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
203 if (!mcf_edma)
206 mcf_edma->n_chans = chans;
209 mcf_edma->drvdata = &mcf_data;
210 mcf_edma->big_endian = 1;
212 mutex_init(&mcf_edma->fsl_edma_mutex);
216 mcf_edma->membase = devm_ioremap_resource(&pdev->dev, res);
217 if (IS_ERR(mcf_edma->membase))
218 return PTR_ERR(mcf_edma->membase);
220 fsl_edma_setup_regs(mcf_edma);
221 regs = &mcf_edma->regs;
223 INIT_LIST_HEAD(&mcf_edma->dma_dev.channels);
224 for (i = 0; i < mcf_edma->n_chans; i++) {
225 struct fsl_edma_chan *mcf_chan = &mcf_edma->chans[i];
227 mcf_chan->edma = mcf_edma;
232 vchan_init(&mcf_chan->vchan, &mcf_edma->dma_dev);
239 ret = mcf_edma->drvdata->setup_irq(pdev, mcf_edma);
243 dma_cap_set(DMA_PRIVATE, mcf_edma->dma_dev.cap_mask);
244 dma_cap_set(DMA_SLAVE, mcf_edma->dma_dev.cap_mask);
245 dma_cap_set(DMA_CYCLIC, mcf_edma->dma_dev.cap_mask);
247 mcf_edma->dma_dev.dev = &pdev->dev;
248 mcf_edma->dma_dev.device_alloc_chan_resources =
250 mcf_edma->dma_dev.device_free_chan_resources =
252 mcf_edma->dma_dev.device_config = fsl_edma_slave_config;
253 mcf_edma->dma_dev.device_prep_dma_cyclic =
255 mcf_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
256 mcf_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
257 mcf_edma->dma_dev.device_pause = fsl_edma_pause;
258 mcf_edma->dma_dev.device_resume = fsl_edma_resume;
259 mcf_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
260 mcf_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
262 mcf_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
263 mcf_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
264 mcf_edma->dma_dev.directions =
267 mcf_edma->dma_dev.filter.fn = mcf_edma_filter_fn;
268 mcf_edma->dma_dev.filter.map = pdata->slave_map;
269 mcf_edma->dma_dev.filter.mapcnt = pdata->slavecnt;
271 platform_set_drvdata(pdev, mcf_edma);
273 ret = dma_async_device_register(&mcf_edma->dma_dev);
288 struct fsl_edma_engine *mcf_edma = platform_get_drvdata(pdev);
290 mcf_edma_irq_free(pdev, mcf_edma);
291 fsl_edma_cleanup_vchan(&mcf_edma->dma_dev);
292 dma_async_device_unregister(&mcf_edma->dma_dev);