Lines Matching refs:dma_dev
223 INIT_LIST_HEAD(&mcf_edma->dma_dev.channels);
232 vchan_init(&mcf_chan->vchan, &mcf_edma->dma_dev);
243 dma_cap_set(DMA_PRIVATE, mcf_edma->dma_dev.cap_mask);
244 dma_cap_set(DMA_SLAVE, mcf_edma->dma_dev.cap_mask);
245 dma_cap_set(DMA_CYCLIC, mcf_edma->dma_dev.cap_mask);
247 mcf_edma->dma_dev.dev = &pdev->dev;
248 mcf_edma->dma_dev.device_alloc_chan_resources =
250 mcf_edma->dma_dev.device_free_chan_resources =
252 mcf_edma->dma_dev.device_config = fsl_edma_slave_config;
253 mcf_edma->dma_dev.device_prep_dma_cyclic =
255 mcf_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
256 mcf_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
257 mcf_edma->dma_dev.device_pause = fsl_edma_pause;
258 mcf_edma->dma_dev.device_resume = fsl_edma_resume;
259 mcf_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
260 mcf_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
262 mcf_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
263 mcf_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
264 mcf_edma->dma_dev.directions =
267 mcf_edma->dma_dev.filter.fn = mcf_edma_filter_fn;
268 mcf_edma->dma_dev.filter.map = pdata->slave_map;
269 mcf_edma->dma_dev.filter.mapcnt = pdata->slavecnt;
273 ret = dma_async_device_register(&mcf_edma->dma_dev);
291 fsl_edma_cleanup_vchan(&mcf_edma->dma_dev);
292 dma_async_device_unregister(&mcf_edma->dma_dev);