Lines Matching defs:base
93 void __iomem *base;
101 void __iomem *base;
139 val = readl_relaxed(phy->base + CX_CFG);
141 writel_relaxed(val, phy->base + CX_CFG);
143 val = readl_relaxed(phy->base + CX_CFG);
145 writel_relaxed(val, phy->base + CX_CFG);
156 writel_relaxed(val, d->base + INT_TC1_RAW);
157 writel_relaxed(val, d->base + INT_TC2_RAW);
158 writel_relaxed(val, d->base + INT_ERR1_RAW);
159 writel_relaxed(val, d->base + INT_ERR2_RAW);
164 writel_relaxed(hw->lli, phy->base + CX_LLI);
165 writel_relaxed(hw->count, phy->base + CX_CNT0);
166 writel_relaxed(hw->saddr, phy->base + CX_SRC);
167 writel_relaxed(hw->daddr, phy->base + CX_DST);
168 writel_relaxed(hw->config, phy->base + CX_CFG);
175 cnt = readl_relaxed(d->base + CX_CUR_CNT + phy->idx * 0x10);
182 return readl_relaxed(phy->base + CX_LLI);
187 return readl_relaxed(d->base + CH_STAT);
194 writel_relaxed(0x0, d->base + CH_PRI);
197 writel_relaxed(0xffff, d->base + INT_TC1_MASK);
198 writel_relaxed(0xffff, d->base + INT_TC2_MASK);
199 writel_relaxed(0xffff, d->base + INT_ERR1_MASK);
200 writel_relaxed(0xffff, d->base + INT_ERR2_MASK);
203 writel_relaxed(0x0, d->base + INT_TC1_MASK);
204 writel_relaxed(0x0, d->base + INT_TC2_MASK);
205 writel_relaxed(0x0, d->base + INT_ERR1_MASK);
206 writel_relaxed(0x0, d->base + INT_ERR2_MASK);
215 u32 stat = readl_relaxed(d->base + INT_STAT);
216 u32 tc1 = readl_relaxed(d->base + INT_TC1);
217 u32 tc2 = readl_relaxed(d->base + INT_TC2);
218 u32 err1 = readl_relaxed(d->base + INT_ERR1);
219 u32 err2 = readl_relaxed(d->base + INT_ERR2);
251 writel_relaxed(irq_chan, d->base + INT_TC1_RAW);
252 writel_relaxed(irq_chan, d->base + INT_TC2_RAW);
253 writel_relaxed(err1, d->base + INT_ERR1_RAW);
254 writel_relaxed(err2, d->base + INT_ERR2_RAW);
854 d->base = devm_platform_ioremap_resource(op, 0);
855 if (IS_ERR(d->base))
856 return PTR_ERR(d->base);
909 p->base = d->base + i * 0x40;