Lines Matching defs:dma_dev
1271 struct dma_device *dma_dev;
1285 dma_dev = &adev->common;
1306 dma_dev->cap_mask = plat_data->cap_mask;
1311 INIT_LIST_HEAD(&dma_dev->channels);
1314 dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources;
1315 dma_dev->device_free_chan_resources = iop_adma_free_chan_resources;
1316 dma_dev->device_tx_status = iop_adma_status;
1317 dma_dev->device_issue_pending = iop_adma_issue_pending;
1318 dma_dev->dev = &pdev->dev;
1321 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1322 dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy;
1323 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1324 dma_dev->max_xor = iop_adma_get_max_xor();
1325 dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor;
1327 if (dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask))
1328 dma_dev->device_prep_dma_xor_val =
1330 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1331 dma_set_maxpq(dma_dev, iop_adma_get_max_pq(), 0);
1332 dma_dev->device_prep_dma_pq = iop_adma_prep_dma_pq;
1334 if (dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask))
1335 dma_dev->device_prep_dma_pq_val =
1337 if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1338 dma_dev->device_prep_dma_interrupt =
1380 iop_chan->common.device = dma_dev;
1382 list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
1384 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1391 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1398 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask) &&
1399 dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask)) {
1405 dma_cap_clear(DMA_PQ, dma_dev->cap_mask);
1406 dma_cap_clear(DMA_PQ_VAL, dma_dev->cap_mask);
1414 dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "",
1415 dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask) ? "pq_val " : "",
1416 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1417 dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask) ? "xor_val " : "",
1418 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1419 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1421 dma_async_device_register(dma_dev);