Lines Matching refs:sdma
3 // drivers/dma/imx-sdma.c
38 #include <linux/platform_data/dma-imx-sdma.h>
247 * struct sdma_context_data - sdma context specific to a channel
334 * @desc: sdma description including vd and other special member
335 * @sdma: pointer to the SDMA engine for this channel
358 * @data: specific sdma interface structure
365 struct sdma_engine *sdma;
570 .name = "imx25-sdma",
573 .name = "imx31-sdma",
576 .name = "imx35-sdma",
579 .name = "imx51-sdma",
582 .name = "imx53-sdma",
585 .name = "imx6q-sdma",
588 .name = "imx7d-sdma",
591 .name = "imx8mq-sdma",
600 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
601 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
602 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
603 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
604 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
605 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
606 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
607 { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
617 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
619 u32 chnenbl0 = sdma->drvdata->chnenbl0;
626 struct sdma_engine *sdma = sdmac->sdma;
633 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
634 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
635 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
652 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
653 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
654 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
659 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
661 writel(BIT(channel), sdma->regs + SDMA_H_START);
667 static int sdma_run_channel0(struct sdma_engine *sdma)
672 sdma_enable_channel(sdma, 0);
674 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
677 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
680 reg = readl(sdma->regs + SDMA_H_CONFIG);
683 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG);
689 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
692 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
698 buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL);
703 spin_lock_irqsave(&sdma->channel_0_lock, flags);
713 ret = sdma_run_channel0(sdma);
715 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
717 dma_free_coherent(sdma->dev, size, buf_virt, buf_phys);
724 struct sdma_engine *sdma = sdmac->sdma;
727 u32 chnenbl = chnenbl_ofs(sdma, event);
729 val = readl_relaxed(sdma->regs + chnenbl);
731 writel_relaxed(val, sdma->regs + chnenbl);
736 struct sdma_engine *sdma = sdmac->sdma;
738 u32 chnenbl = chnenbl_ofs(sdma, event);
741 val = readl_relaxed(sdma->regs + chnenbl);
743 writel_relaxed(val, sdma->regs + chnenbl);
755 struct sdma_engine *sdma = sdmac->sdma;
766 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
767 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
768 sdma_enable_channel(sdma, sdmac->channel);
848 struct sdma_engine *sdma = dev_id;
851 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
852 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
858 struct sdma_channel *sdmac = &sdma->channel[channel];
886 struct sdma_engine *sdma = sdmac->sdma;
901 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
904 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
905 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
908 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
909 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
912 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
913 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
916 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
917 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
920 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
921 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
927 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
928 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
931 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
932 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
940 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
941 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
944 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
945 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
946 per_2_per = sdma->script_addrs->per_2_per_addr;
949 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
950 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
951 per_2_per = sdma->script_addrs->per_2_per_addr;
954 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
955 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
958 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
961 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
962 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
965 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
979 struct sdma_engine *sdma = sdmac->sdma;
982 struct sdma_context_data *context = sdma->context;
983 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
999 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
1000 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
1001 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
1002 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
1003 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
1004 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
1006 spin_lock_irqsave(&sdma->channel_0_lock, flags);
1023 bd0->buffer_addr = sdma->context_phys;
1025 ret = sdma_run_channel0(sdma);
1027 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
1040 struct sdma_engine *sdma = sdmac->sdma;
1043 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
1100 struct sdma_engine *sdma = sdmac->sdma;
1127 if (sdmac->per_address2 >= sdma->spba_start_addr &&
1128 sdmac->per_address2 <= sdma->spba_end_addr)
1131 if (sdmac->per_address >= sdma->spba_start_addr &&
1132 sdmac->per_address <= sdma->spba_end_addr)
1186 struct sdma_engine *sdma = sdmac->sdma;
1194 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1199 static int sdma_request_channel0(struct sdma_engine *sdma)
1203 sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys,
1205 if (!sdma->bd0) {
1210 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
1211 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
1213 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
1226 desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size,
1240 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd,
1269 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n");
1296 ret = clk_enable(sdmac->sdma->clk_ipg);
1299 ret = clk_enable(sdmac->sdma->clk_ahb);
1310 clk_disable(sdmac->sdma->clk_ahb);
1312 clk_disable(sdmac->sdma->clk_ipg);
1319 struct sdma_engine *sdma = sdmac->sdma;
1334 clk_disable(sdma->clk_ipg);
1335 clk_disable(sdma->clk_ahb);
1383 struct sdma_engine *sdma = sdmac->sdma;
1393 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n",
1423 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n",
1440 struct sdma_engine *sdma = sdmac->sdma;
1452 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1464 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1501 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1524 struct sdma_engine *sdma = sdmac->sdma;
1530 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1543 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
1567 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
1626 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1631 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1696 static void sdma_add_scripts(struct sdma_engine *sdma,
1700 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1704 if (!sdma->script_number)
1705 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1707 if (sdma->script_number > sizeof(struct sdma_script_start_addrs)
1709 dev_err(sdma->dev,
1711 sdma->script_number);
1715 for (i = 0; i < sdma->script_number; i++)
1722 struct sdma_engine *sdma = context;
1728 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1744 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1747 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1750 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1753 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1756 dev_err(sdma->dev, "unknown firmware version\n");
1763 clk_enable(sdma->clk_ipg);
1764 clk_enable(sdma->clk_ahb);
1766 sdma_load_script(sdma, ram_code,
1769 clk_disable(sdma->clk_ipg);
1770 clk_disable(sdma->clk_ahb);
1772 sdma_add_scripts(sdma, addr);
1774 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1784 static int sdma_event_remap(struct sdma_engine *sdma)
1786 struct device_node *np = sdma->dev->of_node;
1790 char propname[] = "fsl,sdma-event-remap";
1800 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1803 dev_err(sdma->dev, "the property %s must modulo %d\n",
1811 dev_err(sdma->dev, "failed to get gpr regmap\n");
1819 dev_err(sdma->dev, "failed to read property %s index %d\n",
1826 dev_err(sdma->dev, "failed to read property %s index %d\n",
1833 dev_err(sdma->dev, "failed to read property %s index %d\n",
1848 static int sdma_get_firmware(struct sdma_engine *sdma,
1854 FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1855 GFP_KERNEL, sdma, sdma_load_firmware);
1860 static int sdma_init(struct sdma_engine *sdma)
1865 ret = clk_enable(sdma->clk_ipg);
1868 ret = clk_enable(sdma->clk_ahb);
1872 if (sdma->drvdata->check_ratio &&
1873 (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg)))
1874 sdma->clk_ratio = 1;
1877 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1879 sdma->channel_control = dma_alloc_coherent(sdma->dev,
1884 if (!sdma->channel_control) {
1889 sdma->context = (void *)sdma->channel_control +
1891 sdma->context_phys = ccb_phys +
1895 for (i = 0; i < sdma->drvdata->num_events; i++)
1896 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1900 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1902 ret = sdma_request_channel0(sdma);
1906 sdma_config_ownership(&sdma->channel[0], false, true, false);
1909 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1912 if (sdma->clk_ratio)
1913 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG);
1915 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1917 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1920 sdma_set_channel_priority(&sdma->channel[0], 7);
1922 clk_disable(sdma->clk_ipg);
1923 clk_disable(sdma->clk_ahb);
1928 clk_disable(sdma->clk_ahb);
1930 clk_disable(sdma->clk_ipg);
1931 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1952 struct sdma_engine *sdma = ofdma->of_dma_data;
1953 dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1988 struct sdma_engine *sdma;
2006 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
2007 if (!sdma)
2010 spin_lock_init(&sdma->channel_0_lock);
2012 sdma->dev = &pdev->dev;
2013 sdma->drvdata = drvdata;
2020 sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
2021 if (IS_ERR(sdma->regs))
2022 return PTR_ERR(sdma->regs);
2024 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2025 if (IS_ERR(sdma->clk_ipg))
2026 return PTR_ERR(sdma->clk_ipg);
2028 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2029 if (IS_ERR(sdma->clk_ahb))
2030 return PTR_ERR(sdma->clk_ahb);
2032 ret = clk_prepare(sdma->clk_ipg);
2036 ret = clk_prepare(sdma->clk_ahb);
2040 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
2041 sdma);
2045 sdma->irq = irq;
2047 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
2048 if (!sdma->script_addrs) {
2054 saddr_arr = (s32 *)sdma->script_addrs;
2055 for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++)
2058 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
2059 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
2060 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask);
2062 INIT_LIST_HEAD(&sdma->dma_device.channels);
2065 struct sdma_channel *sdmac = &sdma->channel[i];
2067 sdmac->sdma = sdma;
2076 * that channel 0 in dmaengine counting matches sdma channel 1.
2079 vchan_init(&sdmac->vc, &sdma->dma_device);
2082 ret = sdma_init(sdma);
2086 ret = sdma_event_remap(sdma);
2090 if (sdma->drvdata->script_addrs)
2091 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
2093 sdma_add_scripts(sdma, pdata->script_addrs);
2095 sdma->dma_device.dev = &pdev->dev;
2097 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
2098 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
2099 sdma->dma_device.device_tx_status = sdma_tx_status;
2100 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
2101 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
2102 sdma->dma_device.device_config = sdma_config;
2103 sdma->dma_device.device_terminate_all = sdma_terminate_all;
2104 sdma->dma_device.device_synchronize = sdma_channel_synchronize;
2105 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
2106 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
2107 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
2108 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2109 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy;
2110 sdma->dma_device.device_issue_pending = sdma_issue_pending;
2111 sdma->dma_device.copy_align = 2;
2112 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT);
2114 platform_set_drvdata(pdev, sdma);
2116 ret = dma_async_device_register(&sdma->dma_device);
2123 ret = of_dma_controller_register(np, sdma_xlate, sdma);
2132 sdma->spba_start_addr = spba_res.start;
2133 sdma->spba_end_addr = spba_res.end;
2141 * the firmware callback requires a fully functional and allocated sdma
2145 ret = sdma_get_firmware(sdma, pdata->fw_name);
2154 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
2159 ret = sdma_get_firmware(sdma, fw_name);
2168 dma_async_device_unregister(&sdma->dma_device);
2170 kfree(sdma->script_addrs);
2172 clk_unprepare(sdma->clk_ahb);
2174 clk_unprepare(sdma->clk_ipg);
2180 struct sdma_engine *sdma = platform_get_drvdata(pdev);
2183 devm_free_irq(&pdev->dev, sdma->irq, sdma);
2184 dma_async_device_unregister(&sdma->dma_device);
2185 kfree(sdma->script_addrs);
2186 clk_unprepare(sdma->clk_ahb);
2187 clk_unprepare(sdma->clk_ipg);
2190 struct sdma_channel *sdmac = &sdma->channel[i];
2202 .name = "imx-sdma",
2215 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2218 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");