Lines Matching refs:imxdmac
241 static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
245 if (!list_empty(&imxdmac->ld_active)) {
246 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
267 static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
269 struct imxdma_engine *imxdma = imxdmac->imxdma;
272 return imxdmac->hw_chaining;
282 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
283 struct imxdma_engine *imxdma = imxdmac->imxdma;
293 DMA_DAR(imxdmac->channel));
296 DMA_SAR(imxdmac->channel));
298 imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
301 "size 0x%08x\n", __func__, imxdmac->channel,
302 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
303 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
304 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
309 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
310 struct imxdma_engine *imxdma = imxdmac->imxdma;
311 int channel = imxdmac->channel;
325 d->sg && imxdma_hw_chain(imxdmac)) {
339 static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
341 struct imxdma_engine *imxdma = imxdmac->imxdma;
342 int channel = imxdmac->channel;
347 if (imxdma_hw_chain(imxdmac))
348 del_timer(&imxdmac->watchdog);
361 struct imxdma_channel *imxdmac = from_timer(imxdmac, t, watchdog);
362 struct imxdma_engine *imxdma = imxdmac->imxdma;
363 int channel = imxdmac->channel;
368 tasklet_schedule(&imxdmac->dma_tasklet);
370 imxdmac->channel);
426 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
428 struct imxdma_engine *imxdma = imxdmac->imxdma;
429 int chno = imxdmac->channel;
434 if (list_empty(&imxdmac->ld_active)) {
439 desc = list_first_entry(&imxdmac->ld_active,
453 if (imxdma_hw_chain(imxdmac)) {
457 mod_timer(&imxdmac->watchdog,
470 if (imxdma_chan_is_doing_cyclic(imxdmac))
472 tasklet_schedule(&imxdmac->dma_tasklet);
477 if (imxdma_hw_chain(imxdmac)) {
478 del_timer(&imxdmac->watchdog);
486 tasklet_schedule(&imxdmac->dma_tasklet);
512 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
513 struct imxdma_engine *imxdma = imxdmac->imxdma;
538 imxdmac->slot_2d = slot;
539 imxdmac->enabled_2d = true;
560 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
561 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
563 DMA_CCR(imxdmac->channel));
565 imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
569 __func__, imxdmac->channel,
578 imx_dmav1_writel(imxdma, imxdmac->per_address,
579 DMA_SAR(imxdmac->channel));
580 imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
581 DMA_CCR(imxdmac->channel));
585 __func__, imxdmac->channel,
587 (unsigned long long)imxdmac->per_address);
589 imx_dmav1_writel(imxdma, imxdmac->per_address,
590 DMA_DAR(imxdmac->channel));
591 imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
592 DMA_CCR(imxdmac->channel));
596 __func__, imxdmac->channel,
598 (unsigned long long)imxdmac->per_address);
601 __func__, imxdmac->channel);
617 struct imxdma_channel *imxdmac = from_tasklet(imxdmac, t, dma_tasklet);
618 struct imxdma_engine *imxdma = imxdmac->imxdma;
624 if (list_empty(&imxdmac->ld_active)) {
629 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
635 if (imxdma_chan_is_doing_cyclic(imxdmac))
641 if (imxdmac->enabled_2d) {
642 imxdma->slots_2d[imxdmac->slot_2d].count--;
643 imxdmac->enabled_2d = false;
646 list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
648 if (!list_empty(&imxdmac->ld_queue)) {
649 next_desc = list_first_entry(&imxdmac->ld_queue,
651 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
654 __func__, imxdmac->channel);
664 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
665 struct imxdma_engine *imxdma = imxdmac->imxdma;
668 imxdma_disable_hw(imxdmac);
671 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
672 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
681 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
682 struct imxdma_engine *imxdma = imxdmac->imxdma;
686 imxdmac->per_address = dmaengine_cfg->src_addr;
687 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
688 imxdmac->word_size = dmaengine_cfg->src_addr_width;
690 imxdmac->per_address = dmaengine_cfg->dst_addr;
691 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
692 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
695 switch (imxdmac->word_size) {
708 imxdmac->hw_chaining = 0;
710 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
713 imxdmac->ccr_to_device =
716 imx_dmav1_writel(imxdma, imxdmac->dma_request,
717 DMA_RSSR(imxdmac->channel));
720 imx_dmav1_writel(imxdma, imxdmac->watermark_level *
721 imxdmac->word_size, DMA_BLR(imxdmac->channel));
729 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
731 memcpy(&imxdmac->config, dmaengine_cfg, sizeof(*dmaengine_cfg));
745 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
746 struct imxdma_engine *imxdma = imxdmac->imxdma;
751 list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
760 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
764 imxdmac->dma_request = data->dma_request;
766 while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
779 list_add_tail(&desc->node, &imxdmac->ld_free);
780 imxdmac->descs_allocated++;
783 if (!imxdmac->descs_allocated)
786 return imxdmac->descs_allocated;
791 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
792 struct imxdma_engine *imxdma = imxdmac->imxdma;
798 imxdma_disable_hw(imxdmac);
799 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
800 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
804 list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
806 imxdmac->descs_allocated--;
808 INIT_LIST_HEAD(&imxdmac->ld_free);
810 kfree(imxdmac->sg_list);
811 imxdmac->sg_list = NULL;
819 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
824 if (list_empty(&imxdmac->ld_free) ||
825 imxdma_chan_is_doing_cyclic(imxdmac))
828 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
834 imxdma_config_write(chan, &imxdmac->config, direction);
836 switch (imxdmac->word_size) {
857 desc->src = imxdmac->per_address;
859 desc->dest = imxdmac->per_address;
872 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
873 struct imxdma_engine *imxdma = imxdmac->imxdma;
879 __func__, imxdmac->channel, buf_len, period_len);
881 if (list_empty(&imxdmac->ld_free) ||
882 imxdma_chan_is_doing_cyclic(imxdmac))
885 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
887 kfree(imxdmac->sg_list);
889 imxdmac->sg_list = kcalloc(periods + 1,
891 if (!imxdmac->sg_list)
894 sg_init_table(imxdmac->sg_list, periods);
897 sg_assign_page(&imxdmac->sg_list[i], NULL);
898 imxdmac->sg_list[i].offset = 0;
899 imxdmac->sg_list[i].dma_address = dma_addr;
900 sg_dma_len(&imxdmac->sg_list[i]) = period_len;
905 sg_chain(imxdmac->sg_list, periods + 1, imxdmac->sg_list);
908 desc->sg = imxdmac->sg_list;
913 desc->src = imxdmac->per_address;
915 desc->dest = imxdmac->per_address;
920 imxdma_config_write(chan, &imxdmac->config, direction);
929 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
930 struct imxdma_engine *imxdma = imxdmac->imxdma;
934 __func__, imxdmac->channel, (unsigned long long)src,
937 if (list_empty(&imxdmac->ld_free) ||
938 imxdma_chan_is_doing_cyclic(imxdmac))
941 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
960 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
961 struct imxdma_engine *imxdma = imxdmac->imxdma;
966 imxdmac->channel, (unsigned long long)xt->src_start,
971 if (list_empty(&imxdmac->ld_free) ||
972 imxdma_chan_is_doing_cyclic(imxdmac))
978 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
1002 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
1003 struct imxdma_engine *imxdma = imxdmac->imxdma;
1008 if (list_empty(&imxdmac->ld_active) &&
1009 !list_empty(&imxdmac->ld_queue)) {
1010 desc = list_first_entry(&imxdmac->ld_queue,
1016 __func__, imxdmac->channel);
1018 list_move_tail(imxdmac->ld_queue.next,
1019 &imxdmac->ld_active);
1151 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1163 imxdmac->irq = irq + i;
1164 timer_setup(&imxdmac->watchdog, imxdma_watchdog, 0);
1167 imxdmac->imxdma = imxdma;
1169 INIT_LIST_HEAD(&imxdmac->ld_queue);
1170 INIT_LIST_HEAD(&imxdmac->ld_free);
1171 INIT_LIST_HEAD(&imxdmac->ld_active);
1173 tasklet_setup(&imxdmac->dma_tasklet, imxdma_tasklet);
1174 imxdmac->chan.device = &imxdma->dma_device;
1175 dma_cookie_init(&imxdmac->chan);
1176 imxdmac->channel = i;
1179 list_add_tail(&imxdmac->chan.device_node,
1237 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1240 disable_irq(imxdmac->irq);
1242 tasklet_kill(&imxdmac->dma_tasklet);