Lines Matching refs:mdma
118 struct mdc_dma *mdma;
149 static inline u32 mdc_readl(struct mdc_dma *mdma, u32 reg)
151 return readl(mdma->regs + reg);
154 static inline void mdc_writel(struct mdc_dma *mdma, u32 val, u32 reg)
156 writel(val, mdma->regs + reg);
161 return mdc_readl(mchan->mdma, mchan->chan_nr * 0x040 + reg);
166 mdc_writel(mchan->mdma, val, mchan->chan_nr * 0x040 + reg);
181 static inline struct device *mdma2dev(struct mdc_dma *mdma)
183 return mdma->dma_dev.dev;
210 struct mdc_dma *mdma = mchan->mdma;
229 if (IS_ALIGNED(dst, mdma->bus_width) &&
230 IS_ALIGNED(src, mdma->bus_width))
231 max_burst = mdma->bus_width * mdma->max_burst_mult;
233 max_burst = mdma->bus_width * (mdma->max_burst_mult - 1);
238 mdc_set_read_width(ldesc, mdma->bus_width);
246 mdc_set_write_width(ldesc, mdma->bus_width);
252 mdc_set_read_width(ldesc, mdma->bus_width);
253 mdc_set_write_width(ldesc, mdma->bus_width);
262 struct mdc_dma *mdma = mdesc->chan->mdma;
271 dma_pool_free(mdma->desc_pool, curr, curr_phys);
290 struct mdc_dma *mdma = mchan->mdma;
307 curr = dma_pool_alloc(mdma->desc_pool, GFP_NOWAIT, &curr_phys);
319 xfer_size = min_t(size_t, mdma->max_xfer_size, len);
360 if (width > mchan->mdma->bus_width)
372 struct mdc_dma *mdma = mchan->mdma;
393 mdma->max_xfer_size);
401 curr = dma_pool_alloc(mdma->desc_pool, GFP_NOWAIT,
414 xfer_size = min_t(size_t, mdma->max_xfer_size,
453 struct mdc_dma *mdma = mchan->mdma;
481 curr = dma_pool_alloc(mdma->desc_pool, GFP_NOWAIT,
494 xfer_size = min_t(size_t, mdma->max_xfer_size,
526 struct mdc_dma *mdma = mchan->mdma;
540 dev_dbg(mdma2dev(mdma), "Issuing descriptor on channel %d\n",
543 mdma->soc->enable_chan(mchan);
740 struct device *dev = mdma2dev(mchan->mdma);
748 struct mdc_dma *mdma = mchan->mdma;
749 struct device *dev = mdma2dev(mdma);
752 mdma->soc->disable_chan(mchan);
764 dev_dbg(mdma2dev(mchan->mdma), "IRQ on channel %d\n", mchan->chan_nr);
773 dev_warn(mdma2dev(mchan->mdma),
811 struct mdc_dma *mdma = ofdma->of_dma_data;
817 list_for_each_entry(chan, &mdma->dma_dev.channels, device_node) {
838 struct mdc_dma *mdma = mchan->mdma;
840 regmap_update_bits(mdma->periph_regs,
850 struct mdc_dma *mdma = mchan->mdma;
852 regmap_update_bits(mdma->periph_regs,
872 struct mdc_dma *mdma = dev_get_drvdata(dev);
874 clk_disable_unprepare(mdma->clk);
881 struct mdc_dma *mdma = dev_get_drvdata(dev);
883 return clk_prepare_enable(mdma->clk);
888 struct mdc_dma *mdma;
894 mdma = devm_kzalloc(&pdev->dev, sizeof(*mdma), GFP_KERNEL);
895 if (!mdma)
897 platform_set_drvdata(pdev, mdma);
899 mdma->soc = of_device_get_match_data(&pdev->dev);
902 mdma->regs = devm_ioremap_resource(&pdev->dev, res);
903 if (IS_ERR(mdma->regs))
904 return PTR_ERR(mdma->regs);
906 mdma->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
908 if (IS_ERR(mdma->periph_regs))
909 return PTR_ERR(mdma->periph_regs);
911 mdma->clk = devm_clk_get(&pdev->dev, "sys");
912 if (IS_ERR(mdma->clk))
913 return PTR_ERR(mdma->clk);
915 dma_cap_zero(mdma->dma_dev.cap_mask);
916 dma_cap_set(DMA_SLAVE, mdma->dma_dev.cap_mask);
917 dma_cap_set(DMA_PRIVATE, mdma->dma_dev.cap_mask);
918 dma_cap_set(DMA_CYCLIC, mdma->dma_dev.cap_mask);
919 dma_cap_set(DMA_MEMCPY, mdma->dma_dev.cap_mask);
921 val = mdc_readl(mdma, MDC_GLOBAL_CONFIG_A);
922 mdma->nr_channels = (val >> MDC_GLOBAL_CONFIG_A_DMA_CONTEXTS_SHIFT) &
924 mdma->nr_threads =
927 mdma->bus_width =
939 mdma->max_xfer_size = MDC_TRANSFER_SIZE_MASK + 1 - mdma->bus_width;
942 &mdma->nr_channels);
945 &mdma->max_burst_mult);
949 mdma->dma_dev.dev = &pdev->dev;
950 mdma->dma_dev.device_prep_slave_sg = mdc_prep_slave_sg;
951 mdma->dma_dev.device_prep_dma_cyclic = mdc_prep_dma_cyclic;
952 mdma->dma_dev.device_prep_dma_memcpy = mdc_prep_dma_memcpy;
953 mdma->dma_dev.device_alloc_chan_resources = mdc_alloc_chan_resources;
954 mdma->dma_dev.device_free_chan_resources = mdc_free_chan_resources;
955 mdma->dma_dev.device_tx_status = mdc_tx_status;
956 mdma->dma_dev.device_issue_pending = mdc_issue_pending;
957 mdma->dma_dev.device_terminate_all = mdc_terminate_all;
958 mdma->dma_dev.device_synchronize = mdc_synchronize;
959 mdma->dma_dev.device_config = mdc_slave_config;
961 mdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
962 mdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
963 for (i = 1; i <= mdma->bus_width; i <<= 1) {
964 mdma->dma_dev.src_addr_widths |= BIT(i);
965 mdma->dma_dev.dst_addr_widths |= BIT(i);
968 INIT_LIST_HEAD(&mdma->dma_dev.channels);
969 for (i = 0; i < mdma->nr_channels; i++) {
970 struct mdc_chan *mchan = &mdma->channels[i];
972 mchan->mdma = mdma;
985 vchan_init(&mchan->vc, &mdma->dma_dev);
988 mdma->desc_pool = dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
991 if (!mdma->desc_pool)
1001 ret = dma_async_device_register(&mdma->dma_dev);
1005 ret = of_dma_controller_register(pdev->dev.of_node, mdc_of_xlate, mdma);
1010 mdma->nr_channels, mdma->nr_threads);
1015 dma_async_device_unregister(&mdma->dma_dev);
1025 struct mdc_dma *mdma = platform_get_drvdata(pdev);
1029 dma_async_device_unregister(&mdma->dma_dev);
1031 list_for_each_entry_safe(mchan, next, &mdma->dma_dev.channels,
1050 struct mdc_dma *mdma = dev_get_drvdata(dev);
1054 for (i = 0; i < mdma->nr_channels; i++) {
1055 struct mdc_chan *mchan = &mdma->channels[i];